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target/loongarch: Implement vadd/vsub
This patch includes: - VADD.{B/H/W/D/Q}; - VSUB.{B/H/W/D/Q}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-5-gaosong@loongson.cn>
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@ -14,3 +14,72 @@
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#else
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#define CHECK_SXE
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#endif
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static bool gen_vvv(DisasContext *ctx, arg_vvv *a,
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void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
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{
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TCGv_i32 vd = tcg_constant_i32(a->vd);
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TCGv_i32 vj = tcg_constant_i32(a->vj);
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TCGv_i32 vk = tcg_constant_i32(a->vk);
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CHECK_SXE;
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func(cpu_env, vd, vj, vk);
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return true;
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}
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static bool gvec_vvv(DisasContext *ctx, arg_vvv *a, MemOp mop,
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void (*func)(unsigned, uint32_t, uint32_t,
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uint32_t, uint32_t, uint32_t))
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{
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uint32_t vd_ofs, vj_ofs, vk_ofs;
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CHECK_SXE;
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vd_ofs = vec_full_offset(a->vd);
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vj_ofs = vec_full_offset(a->vj);
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vk_ofs = vec_full_offset(a->vk);
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func(mop, vd_ofs, vj_ofs, vk_ofs, 16, ctx->vl/8);
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return true;
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}
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TRANS(vadd_b, gvec_vvv, MO_8, tcg_gen_gvec_add)
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TRANS(vadd_h, gvec_vvv, MO_16, tcg_gen_gvec_add)
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TRANS(vadd_w, gvec_vvv, MO_32, tcg_gen_gvec_add)
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TRANS(vadd_d, gvec_vvv, MO_64, tcg_gen_gvec_add)
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#define VADDSUB_Q(NAME) \
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static bool trans_v## NAME ##_q(DisasContext *ctx, arg_vvv *a) \
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{ \
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TCGv_i64 rh, rl, ah, al, bh, bl; \
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\
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CHECK_SXE; \
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\
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rh = tcg_temp_new_i64(); \
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rl = tcg_temp_new_i64(); \
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ah = tcg_temp_new_i64(); \
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al = tcg_temp_new_i64(); \
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bh = tcg_temp_new_i64(); \
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bl = tcg_temp_new_i64(); \
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\
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get_vreg64(ah, a->vj, 1); \
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get_vreg64(al, a->vj, 0); \
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get_vreg64(bh, a->vk, 1); \
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get_vreg64(bl, a->vk, 0); \
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\
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tcg_gen_## NAME ##2_i64(rl, rh, al, ah, bl, bh); \
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\
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set_vreg64(rh, a->vd, 1); \
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set_vreg64(rl, a->vd, 0); \
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\
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return true; \
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}
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VADDSUB_Q(add)
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VADDSUB_Q(sub)
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TRANS(vsub_b, gvec_vvv, MO_8, tcg_gen_gvec_sub)
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TRANS(vsub_h, gvec_vvv, MO_16, tcg_gen_gvec_sub)
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TRANS(vsub_w, gvec_vvv, MO_32, tcg_gen_gvec_sub)
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TRANS(vsub_d, gvec_vvv, MO_64, tcg_gen_gvec_sub)
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