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RISC-V: Adding XTheadFmv ISA extension

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This patch adds support for the XTheadFmv ISA extension.
The patch uses the T-Head specific decoder and translation.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-14-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner 2023-01-31 21:20:12 +01:00 • committed by Alistair Francis
parent 95bd8daaaf
commit 578086ba2f
5 changed files with 55 additions and 3 deletions
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45
target/riscv/insn_trans/trans_xthead.c.inc
View file

@ -52,6 +52,12 @@
} \
} while (0)
#define REQUIRE_XTHEADFMV(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadfmv) { \
return false; \
} \
} while (0)
#define REQUIRE_XTHEADMAC(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadmac) { \
return false; \
@ -449,6 +455,45 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a)
return gen_fstore_idx(ctx, a, MO_TEUL, true);
}
/* XTheadFmv */
static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a)
{
REQUIRE_XTHEADFMV(ctx);
REQUIRE_32BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
TCGv_i64 t1 = tcg_temp_new_i64();
tcg_gen_extu_tl_i64(t1, src1);
tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32);
tcg_temp_free_i64(t1);
mark_fs_dirty(ctx);
return true;
}
static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a)
{
REQUIRE_XTHEADFMV(ctx);
REQUIRE_32BIT(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
TCGv dst;
TCGv_i64 t1;
dst = dest_gpr(ctx, a->rd);
t1 = tcg_temp_new_i64();
tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32);
tcg_gen_trunc_i64_tl(dst, t1);
gen_set_gpr(ctx, a->rd, dst);
tcg_temp_free_i64(t1);
mark_fs_dirty(ctx);
return true;
}
/* XTheadMac */
static bool gen_th_mac(DisasContext *ctx, arg_r *a,