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target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test

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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181016223115.24100-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-10-24 07:50:17 +01:00 • committed by Peter Maydell
parent cd208a1c39
commit 5763190fa8
6 changed files with 50 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

40
target/arm/translate-a64.c
View file

@ -4811,7 +4811,7 @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
break;
case 3:
size = MO_16;
if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
/* fallthru */
@ -4862,7 +4862,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
break;
case 3:
size = MO_16;
if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
/* fallthru */
@ -4928,7 +4928,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
break;
case 3:
sz = MO_16;
if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
/* fallthru */
@ -5261,7 +5261,7 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
handle_fp_1src_double(s, opcode, rd, rn);
break;
case 3:
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
}
@ -5476,7 +5476,7 @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
handle_fp_2src_double(s, opcode, rd, rn, rm);
break;
case 3:
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
}
@ -5634,7 +5634,7 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
break;
case 3:
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
}
@ -5704,7 +5704,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
break;
case 3:
sz = MO_16;
if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
/* fallthru */
@ -5929,7 +5929,7 @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
case 1: /* float64 */
break;
case 3: /* float16 */
if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
/* fallthru */
@ -6059,7 +6059,7 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
break;
case 0x6: /* 16-bit float, 32-bit int */
case 0xe: /* 16-bit float, 64-bit int */
if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
/* fallthru */
@ -6086,7 +6086,7 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
case 1: /* float64 */
break;
case 3: /* float16 */
if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (dc_isar_feature(aa64_fp16, s)) {
break;
}
/* fallthru */
@ -6523,7 +6523,7 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
*/
is_min = extract32(size, 1, 1);
is_fp = true;
if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (!is_u && dc_isar_feature(aa64_fp16, s)) {
size = 1;
} else if (!is_u || !is_q || extract32(size, 0, 1)) {
unallocated_encoding(s);
@ -6919,7 +6919,7 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
/* Check for FMOV (vector, immediate) - half-precision */
if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode == 0xf)) {
if (!(dc_isar_feature(aa64_fp16, s) && o2 && cmode == 0xf)) {
unallocated_encoding(s);
return;
}
@ -7086,7 +7086,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
case 0x2f: /* FMINP */
/* FP op, size[0] is 32 or 64 bit*/
if (!u) {
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
} else {
@ -7731,7 +7731,7 @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
size = MO_32;
} else if (immh & 2) {
size = MO_16;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
}
@ -7776,7 +7776,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
size = MO_32;
} else if (immh & 0x2) {
size = MO_16;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
}
@ -8540,7 +8540,7 @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
return;
}
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
}
@ -11221,7 +11221,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
TCGv_ptr fpst;
bool pairwise = false;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
}
@ -11436,7 +11436,7 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
case 0x1c: /* FCADD, #90 */
case 0x1e: /* FCADD, #270 */
if (size == 0
|| (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))
|| (size == 1 && !dc_isar_feature(aa64_fp16, s))
|| (size == 3 && !is_q)) {
unallocated_encoding(s);
return;
@ -12316,7 +12316,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
bool need_fpst = true;
int rmode;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
}
@ -12733,7 +12733,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
}
break;
}
if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
if (is_fp16 && !dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
}