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https://github.com/Motorhead1991/qemu.git
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target/ppc: Drop tcg_temp_free
Translators are no longer required to free tcg temporaries. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
de599a3df3
commit
571f850722
9 changed files with 7 additions and 1094 deletions
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@ -21,7 +21,6 @@ static void gen_set_cr1_from_fpscr(DisasContext *ctx)
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
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tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
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tcg_temp_free_i32(tmp);
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}
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#else
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static void gen_set_cr1_from_fpscr(DisasContext *ctx)
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@ -58,10 +57,6 @@ static void gen_f##name(DisasContext *ctx) \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_i64(t0); \
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tcg_temp_free_i64(t1); \
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tcg_temp_free_i64(t2); \
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tcg_temp_free_i64(t3); \
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}
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#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
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@ -92,9 +87,6 @@ static void gen_f##name(DisasContext *ctx) \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_i64(t0); \
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tcg_temp_free_i64(t1); \
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tcg_temp_free_i64(t2); \
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}
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#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
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_GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); \
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@ -124,9 +116,6 @@ static void gen_f##name(DisasContext *ctx) \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_i64(t0); \
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tcg_temp_free_i64(t1); \
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tcg_temp_free_i64(t2); \
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}
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#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
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_GEN_FLOAT_AC(name, 0x3F, op2, inval, set_fprf, type); \
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@ -154,8 +143,6 @@ static void gen_f##name(DisasContext *ctx) \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_i64(t0); \
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tcg_temp_free_i64(t1); \
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}
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#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
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@ -179,8 +166,6 @@ static void gen_f##name(DisasContext *ctx) \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_i64(t0); \
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tcg_temp_free_i64(t1); \
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}
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/* fadd - fadds */
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@ -218,8 +203,6 @@ static void gen_frsqrtes(DisasContext *ctx)
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if (unlikely(Rc(ctx->opcode) != 0)) {
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gen_set_cr1_from_fpscr(ctx);
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}
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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static bool trans_FSEL(DisasContext *ctx, arg_A *a)
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@ -242,11 +225,6 @@ static bool trans_FSEL(DisasContext *ctx, arg_A *a)
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if (a->rc) {
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gen_set_cr1_from_fpscr(ctx);
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}
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(t2);
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return true;
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}
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@ -273,10 +251,6 @@ static bool do_helper_fsqrt(DisasContext *ctx, arg_A_tb *a,
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if (unlikely(a->rc != 0)) {
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gen_set_cr1_from_fpscr(ctx);
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}
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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return true;
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}
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@ -343,8 +317,6 @@ static void gen_ftdiv(DisasContext *ctx)
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get_fpr(t0, rA(ctx->opcode));
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get_fpr(t1, rB(ctx->opcode));
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gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], t0, t1);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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static void gen_ftsqrt(DisasContext *ctx)
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@ -357,7 +329,6 @@ static void gen_ftsqrt(DisasContext *ctx)
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t0 = tcg_temp_new_i64();
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get_fpr(t0, rB(ctx->opcode));
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gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], t0);
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tcg_temp_free_i64(t0);
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}
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@ -381,10 +352,7 @@ static void gen_fcmpo(DisasContext *ctx)
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get_fpr(t0, rA(ctx->opcode));
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get_fpr(t1, rB(ctx->opcode));
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gen_helper_fcmpo(cpu_env, t0, t1, crf);
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tcg_temp_free_i32(crf);
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gen_helper_float_check_status(cpu_env);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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/* fcmpu */
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@ -404,10 +372,7 @@ static void gen_fcmpu(DisasContext *ctx)
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get_fpr(t0, rA(ctx->opcode));
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get_fpr(t1, rB(ctx->opcode));
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gen_helper_fcmpu(cpu_env, t0, t1, crf);
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tcg_temp_free_i32(crf);
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gen_helper_float_check_status(cpu_env);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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/*** Floating-point move ***/
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@ -429,8 +394,6 @@ static void gen_fabs(DisasContext *ctx)
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if (unlikely(Rc(ctx->opcode))) {
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gen_set_cr1_from_fpscr(ctx);
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}
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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/* fmr - fmr. */
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@ -448,7 +411,6 @@ static void gen_fmr(DisasContext *ctx)
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if (unlikely(Rc(ctx->opcode))) {
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gen_set_cr1_from_fpscr(ctx);
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}
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tcg_temp_free_i64(t0);
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}
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/* fnabs */
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@ -469,8 +431,6 @@ static void gen_fnabs(DisasContext *ctx)
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if (unlikely(Rc(ctx->opcode))) {
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gen_set_cr1_from_fpscr(ctx);
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}
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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/* fneg */
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@ -491,8 +451,6 @@ static void gen_fneg(DisasContext *ctx)
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if (unlikely(Rc(ctx->opcode))) {
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gen_set_cr1_from_fpscr(ctx);
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}
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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/* fcpsgn: PowerPC 2.05 specification */
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@ -516,9 +474,6 @@ static void gen_fcpsgn(DisasContext *ctx)
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if (unlikely(Rc(ctx->opcode))) {
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gen_set_cr1_from_fpscr(ctx);
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}
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(t2);
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}
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static void gen_fmrgew(DisasContext *ctx)
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@ -538,9 +493,6 @@ static void gen_fmrgew(DisasContext *ctx)
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get_fpr(t0, rA(ctx->opcode));
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tcg_gen_deposit_i64(t1, t0, b0, 0, 32);
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set_fpr(rD(ctx->opcode), t1);
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tcg_temp_free_i64(b0);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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static void gen_fmrgow(DisasContext *ctx)
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@ -559,9 +511,6 @@ static void gen_fmrgow(DisasContext *ctx)
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get_fpr(t1, rA(ctx->opcode));
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tcg_gen_deposit_i64(t2, t0, t1, 32, 32);
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set_fpr(rD(ctx->opcode), t2);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(t2);
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}
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/*** Floating-Point status & ctrl register ***/
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@ -587,7 +536,6 @@ static void gen_mcrfs(DisasContext *ctx)
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tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
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tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],
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0xf);
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tcg_temp_free(tmp);
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tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
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/* Only the exception bits (including FX) should be cleared if read */
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tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr,
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@ -595,8 +543,6 @@ static void gen_mcrfs(DisasContext *ctx)
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/* FEX and VX need to be updated, so don't set fpscr directly */
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tmask = tcg_const_i32(1 << nibble);
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gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
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tcg_temp_free_i32(tmask);
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tcg_temp_free_i64(tnew_fpscr);
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}
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static TCGv_i64 place_from_fpscr(int rt, uint64_t mask)
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@ -608,8 +554,6 @@ static TCGv_i64 place_from_fpscr(int rt, uint64_t mask)
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tcg_gen_andi_i64(fpscr_masked, fpscr, mask);
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set_fpr(rt, fpscr_masked);
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tcg_temp_free_i64(fpscr_masked);
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return fpscr;
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}
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@ -622,24 +566,17 @@ static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t clear_mask,
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tcg_gen_andi_i64(fpscr_masked, fpscr, ~clear_mask);
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tcg_gen_or_i64(fpscr_masked, fpscr_masked, set_mask);
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gen_helper_store_fpscr(cpu_env, fpscr_masked, st_mask);
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tcg_temp_free_i64(fpscr_masked);
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}
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static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a)
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{
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TCGv_i64 fpscr;
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REQUIRE_FPU(ctx);
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gen_reset_fpstatus();
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fpscr = place_from_fpscr(a->rt, UINT64_MAX);
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place_from_fpscr(a->rt, UINT64_MAX);
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if (a->rc) {
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gen_set_cr1_from_fpscr(ctx);
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}
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tcg_temp_free_i64(fpscr);
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return true;
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}
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@ -653,9 +590,6 @@ static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a)
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gen_reset_fpstatus();
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fpscr = place_from_fpscr(a->rt, UINT64_MAX);
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store_fpscr_masked(fpscr, FP_ENABLES, tcg_constant_i64(0), 0x0003);
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tcg_temp_free_i64(fpscr);
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return true;
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}
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@ -673,10 +607,6 @@ static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a)
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gen_reset_fpstatus();
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fpscr = place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN);
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store_fpscr_masked(fpscr, FP_RN, t1, 0x0001);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(fpscr);
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return true;
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}
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@ -694,10 +624,6 @@ static bool trans_MFFSCDRN(DisasContext *ctx, arg_X_tb *a)
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gen_reset_fpstatus();
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fpscr = place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN);
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store_fpscr_masked(fpscr, FP_DRN, t1, 0x0100);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(fpscr);
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return true;
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}
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@ -714,10 +640,6 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a)
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gen_reset_fpstatus();
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fpscr = place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN);
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store_fpscr_masked(fpscr, FP_RN, t1, 0x0001);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(fpscr);
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return true;
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}
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@ -734,26 +656,16 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a)
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gen_reset_fpstatus();
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fpscr = place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN);
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store_fpscr_masked(fpscr, FP_DRN, t1, 0x0100);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(fpscr);
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return true;
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}
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static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a)
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{
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TCGv_i64 fpscr;
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REQUIRE_INSNS_FLAGS2(ctx, ISA300);
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REQUIRE_FPU(ctx);
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gen_reset_fpstatus();
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fpscr = place_from_fpscr(a->rt,
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FP_DRN | FP_STATUS | FP_ENABLES | FP_NI | FP_RN);
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tcg_temp_free_i64(fpscr);
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place_from_fpscr(a->rt, FP_DRN | FP_STATUS | FP_ENABLES | FP_NI | FP_RN);
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return true;
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}
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@ -772,7 +684,6 @@ static void gen_mtfsb0(DisasContext *ctx)
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TCGv_i32 t0;
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t0 = tcg_const_i32(crb);
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gen_helper_fpscr_clrbit(cpu_env, t0);
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tcg_temp_free_i32(t0);
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}
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if (unlikely(Rc(ctx->opcode) != 0)) {
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tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
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@ -795,7 +706,6 @@ static void gen_mtfsb1(DisasContext *ctx)
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TCGv_i32 t0;
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t0 = tcg_const_i32(crb);
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gen_helper_fpscr_setbit(cpu_env, t0);
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tcg_temp_free_i32(t0);
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}
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if (unlikely(Rc(ctx->opcode) != 0)) {
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tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
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@ -831,14 +741,12 @@ static void gen_mtfsf(DisasContext *ctx)
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t1 = tcg_temp_new_i64();
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get_fpr(t1, rB(ctx->opcode));
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gen_helper_store_fpscr(cpu_env, t1, t0);
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tcg_temp_free_i32(t0);
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if (unlikely(Rc(ctx->opcode) != 0)) {
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tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
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tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
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}
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/* We can raise a deferred exception */
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gen_helper_fpscr_check_status(cpu_env);
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tcg_temp_free_i64(t1);
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}
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/* mtfsfi */
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@ -862,8 +770,6 @@ static void gen_mtfsfi(DisasContext *ctx)
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t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
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t1 = tcg_const_i32(1 << sh);
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gen_helper_store_fpscr(cpu_env, t0, t1);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i32(t1);
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if (unlikely(Rc(ctx->opcode) != 0)) {
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tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
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tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
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@ -877,7 +783,6 @@ static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_qemu_ld_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL));
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gen_helper_todouble(dest, tmp);
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tcg_temp_free_i32(tmp);
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}
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/* lfdepx (external PID lfdx) */
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@ -896,8 +801,6 @@ static void gen_lfdepx(DisasContext *ctx)
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gen_addr_reg_index(ctx, EA);
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tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UQ));
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set_fpr(rD(ctx->opcode), t0);
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tcg_temp_free(EA);
|
||||
tcg_temp_free_i64(t0);
|
||||
}
|
||||
|
||||
/* lfdp */
|
||||
|
|
@ -930,8 +833,6 @@ static void gen_lfdp(DisasContext *ctx)
|
|||
gen_qemu_ld64_i64(ctx, t0, EA);
|
||||
set_fpr(rD(ctx->opcode) + 1, t0);
|
||||
}
|
||||
tcg_temp_free(EA);
|
||||
tcg_temp_free_i64(t0);
|
||||
}
|
||||
|
||||
/* lfdpx */
|
||||
|
|
@ -964,8 +865,6 @@ static void gen_lfdpx(DisasContext *ctx)
|
|||
gen_qemu_ld64_i64(ctx, t0, EA);
|
||||
set_fpr(rD(ctx->opcode) + 1, t0);
|
||||
}
|
||||
tcg_temp_free(EA);
|
||||
tcg_temp_free_i64(t0);
|
||||
}
|
||||
|
||||
/* lfiwax */
|
||||
|
|
@ -986,9 +885,6 @@ static void gen_lfiwax(DisasContext *ctx)
|
|||
gen_qemu_ld32s(ctx, t0, EA);
|
||||
tcg_gen_ext_tl_i64(t1, t0);
|
||||
set_fpr(rD(ctx->opcode), t1);
|
||||
tcg_temp_free(EA);
|
||||
tcg_temp_free(t0);
|
||||
tcg_temp_free_i64(t1);
|
||||
}
|
||||
|
||||
/* lfiwzx */
|
||||
|
|
@ -1006,8 +902,6 @@ static void gen_lfiwzx(DisasContext *ctx)
|
|||
gen_addr_reg_index(ctx, EA);
|
||||
gen_qemu_ld32u_i64(ctx, t0, EA);
|
||||
set_fpr(rD(ctx->opcode), t0);
|
||||
tcg_temp_free(EA);
|
||||
tcg_temp_free_i64(t0);
|
||||
}
|
||||
|
||||
#define GEN_STXF(name, stop, opc2, opc3, type) \
|
||||
|
|
@ -1025,8 +919,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
|
|||
gen_addr_reg_index(ctx, EA); \
|
||||
get_fpr(t0, rS(ctx->opcode)); \
|
||||
gen_qemu_##stop(ctx, t0, EA); \
|
||||
tcg_temp_free(EA); \
|
||||
tcg_temp_free_i64(t0); \
|
||||
}
|
||||
|
||||
static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
|
||||
|
|
@ -1034,7 +926,6 @@ static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
|
|||
TCGv_i32 tmp = tcg_temp_new_i32();
|
||||
gen_helper_tosingle(tmp, src);
|
||||
tcg_gen_qemu_st_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL));
|
||||
tcg_temp_free_i32(tmp);
|
||||
}
|
||||
|
||||
/* stfdepx (external PID lfdx) */
|
||||
|
|
@ -1053,8 +944,6 @@ static void gen_stfdepx(DisasContext *ctx)
|
|||
gen_addr_reg_index(ctx, EA);
|
||||
get_fpr(t0, rD(ctx->opcode));
|
||||
tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_UQ));
|
||||
tcg_temp_free(EA);
|
||||
tcg_temp_free_i64(t0);
|
||||
}
|
||||
|
||||
/* stfdp */
|
||||
|
|
@ -1087,8 +976,6 @@ static void gen_stfdp(DisasContext *ctx)
|
|||
get_fpr(t0, rD(ctx->opcode) + 1);
|
||||
gen_qemu_st64_i64(ctx, t0, EA);
|
||||
}
|
||||
tcg_temp_free(EA);
|
||||
tcg_temp_free_i64(t0);
|
||||
}
|
||||
|
||||
/* stfdpx */
|
||||
|
|
@ -1121,8 +1008,6 @@ static void gen_stfdpx(DisasContext *ctx)
|
|||
get_fpr(t0, rD(ctx->opcode) + 1);
|
||||
gen_qemu_st64_i64(ctx, t0, EA);
|
||||
}
|
||||
tcg_temp_free(EA);
|
||||
tcg_temp_free_i64(t0);
|
||||
}
|
||||
|
||||
/* Optional: */
|
||||
|
|
@ -1131,7 +1016,6 @@ static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
|
|||
TCGv t0 = tcg_temp_new();
|
||||
tcg_gen_trunc_i64_tl(t0, arg1),
|
||||
gen_qemu_st32(ctx, t0, arg2);
|
||||
tcg_temp_free(t0);
|
||||
}
|
||||
/* stfiwx */
|
||||
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
|
||||
|
|
@ -1169,8 +1053,6 @@ static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ,
|
|||
if (update) {
|
||||
tcg_gen_mov_tl(cpu_gpr[ra], ea);
|
||||
}
|
||||
tcg_temp_free_i64(t0);
|
||||
tcg_temp_free(ea);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue