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target/avr: Add instruction translation - Bit and Bit-test Instructions

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This includes:
    - LSR, ROR
    - ASR
    - SWAP
    - SBI, CBI
    - BST, BLD
    - BSET, BCLR

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-15-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Michael Rolnik 2020-01-24 01:51:13 +01:00 • committed by Philippe Mathieu-Daudé
parent 9732b024f7
commit 5718cef05a
2 changed files with 261 additions and 0 deletions
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14
target/avr/insn.decode
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@ -163,3 +163,17 @@ XCH 1001 001 rd:5 0100
LAC 1001 001 rd:5 0110
LAS 1001 001 rd:5 0101
LAT 1001 001 rd:5 0111
#
# Bit and Bit-test Instructions
#
LSR 1001 010 rd:5 0110
ROR 1001 010 rd:5 0111
ASR 1001 010 rd:5 0101
SWAP 1001 010 rd:5 0010
SBI 1001 1010 reg:5 bit:3
CBI 1001 1000 reg:5 bit:3
BST 1111 101 rd:5 0 bit:3
BLD 1111 100 rd:5 0 bit:3
BSET 1001 0100 0 bit:3 1000
BCLR 1001 0100 1 bit:3 1000