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ppc/ppc405: Activate MMU logs
There is no need to deactivate MMU logging at compile time. Remove all use of defines. Only keep DUMP_PAGE_TABLES for another series since page tables could be dumped from the monitor. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211222064025.1541490-4-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103063441.3424853-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Cédric Le Goater
parent
b3b5c5d38f
commit
56964585a0
2 changed files with 122 additions and 139 deletions
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@ -36,23 +36,8 @@
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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/* #define DEBUG_BATS */
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/* #define DEBUG_SOFTWARE_TLB */
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/* #define DUMP_PAGE_TABLES */
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/* #define FLUSH_ALL_TLBS */
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#ifdef DEBUG_SOFTWARE_TLB
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# define LOG_SWTLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
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#else
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# define LOG_SWTLB(...) do { } while (0)
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#endif
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#ifdef DEBUG_BATS
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# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
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#else
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# define LOG_BATS(...) do { } while (0)
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#endif
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/*****************************************************************************/
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/* PowerPC MMU emulation */
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@ -89,8 +74,8 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
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nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
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tlb = &env->tlb.tlb6[nr];
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if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
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LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
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env->nb_tlb, eaddr);
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qemu_log_mask(CPU_LOG_MMU, "TLB invalidate %d/%d "
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TARGET_FMT_lx "\n", nr, env->nb_tlb, eaddr);
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pte_invalidate(&tlb->pte0);
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tlb_flush_page(cs, tlb->EPN);
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}
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@ -115,8 +100,9 @@ static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way,
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nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
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tlb = &env->tlb.tlb6[nr];
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LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
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" PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
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qemu_log_mask(CPU_LOG_MMU, "Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 "
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TARGET_FMT_lx " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb,
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EPN, pte0, pte1);
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/* Invalidate any pending reference in QEMU for this virtual address */
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ppc6xx_tlb_invalidate_virt2(env, EPN, is_code, 1);
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tlb->pte0 = pte0;
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@ -204,25 +190,27 @@ static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
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end = base + mask + 0x00020000;
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if (((end - base) >> TARGET_PAGE_BITS) > 1024) {
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/* Flushing 1024 4K pages is slower than a complete flush */
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LOG_BATS("Flush all BATs\n");
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qemu_log_mask(CPU_LOG_MMU, "Flush all BATs\n");
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tlb_flush(cs);
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LOG_BATS("Flush done\n");
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qemu_log_mask(CPU_LOG_MMU, "Flush done\n");
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return;
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}
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LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
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TARGET_FMT_lx ")\n", base, end, mask);
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qemu_log_mask(CPU_LOG_MMU, "Flush BAT from " TARGET_FMT_lx
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" to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n",
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base, end, mask);
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for (page = base; page != end; page += TARGET_PAGE_SIZE) {
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tlb_flush_page(cs, page);
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}
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LOG_BATS("Flush done\n");
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qemu_log_mask(CPU_LOG_MMU, "Flush done\n");
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}
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#endif
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static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
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target_ulong value)
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{
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LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID,
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nr, ul == 0 ? 'u' : 'l', value, env->nip);
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qemu_log_mask(CPU_LOG_MMU, "Set %cBAT%d%c to " TARGET_FMT_lx " ("
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TARGET_FMT_lx ")\n", ID, nr, ul == 0 ? 'u' : 'l',
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value, env->nip);
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}
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void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value)
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@ -550,9 +538,9 @@ static void do_6xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code)
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}
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way = (env->spr[SPR_SRR1] >> 17) & 1;
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(void)EPN; /* avoid a compiler warning */
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LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
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" PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP,
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RPN, way);
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qemu_log_mask(CPU_LOG_MMU, "%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx
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" PTE0 " TARGET_FMT_lx " PTE1 " TARGET_FMT_lx " way %d\n",
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__func__, new_EPN, EPN, CMP, RPN, way);
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/* Store this TLB */
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ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
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way, is_code, CMP, RPN);
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@ -721,15 +709,17 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
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ppcemb_tlb_t *tlb;
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target_ulong page, end;
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LOG_SWTLB("%s entry %d val " TARGET_FMT_lx "\n", __func__, (int)entry,
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qemu_log_mask(CPU_LOG_MMU, "%s entry %d val " TARGET_FMT_lx "\n",
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__func__, (int)entry,
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val);
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entry &= PPC4XX_TLB_ENTRY_MASK;
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tlb = &env->tlb.tlbe[entry];
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/* Invalidate previous TLB (if it's valid) */
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if (tlb->prot & PAGE_VALID) {
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end = tlb->EPN + tlb->size;
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LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end "
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TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
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qemu_log_mask(CPU_LOG_MMU, "%s: invalidate old TLB %d start "
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TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__,
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(int)entry, tlb->EPN, end);
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for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
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tlb_flush_page(cs, page);
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}
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@ -758,18 +748,20 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
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tlb->prot &= ~PAGE_VALID;
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}
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tlb->PID = env->spr[SPR_40x_PID]; /* PID */
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LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
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" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
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(int)entry, tlb->RPN, tlb->EPN, tlb->size,
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tlb->prot & PAGE_READ ? 'r' : '-',
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tlb->prot & PAGE_WRITE ? 'w' : '-',
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tlb->prot & PAGE_EXEC ? 'x' : '-',
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tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
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qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx
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" EPN " TARGET_FMT_lx " size " TARGET_FMT_lx
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" prot %c%c%c%c PID %d\n", __func__,
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(int)entry, tlb->RPN, tlb->EPN, tlb->size,
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tlb->prot & PAGE_READ ? 'r' : '-',
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tlb->prot & PAGE_WRITE ? 'w' : '-',
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tlb->prot & PAGE_EXEC ? 'x' : '-',
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tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
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/* Invalidate new TLB (if valid) */
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if (tlb->prot & PAGE_VALID) {
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end = tlb->EPN + tlb->size;
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LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end "
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TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
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qemu_log_mask(CPU_LOG_MMU, "%s: invalidate TLB %d start "
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TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__,
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(int)entry, tlb->EPN, end);
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for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
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tlb_flush_page(cs, page);
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}
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@ -781,8 +773,8 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry,
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{
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ppcemb_tlb_t *tlb;
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LOG_SWTLB("%s entry %i val " TARGET_FMT_lx "\n", __func__, (int)entry,
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val);
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qemu_log_mask(CPU_LOG_MMU, "%s entry %i val " TARGET_FMT_lx "\n",
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__func__, (int)entry, val);
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entry &= PPC4XX_TLB_ENTRY_MASK;
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tlb = &env->tlb.tlbe[entry];
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tlb->attr = val & PPC4XX_TLBLO_ATTR_MASK;
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@ -794,13 +786,14 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry,
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if (val & PPC4XX_TLBLO_WR) {
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tlb->prot |= PAGE_WRITE;
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}
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LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
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" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
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(int)entry, tlb->RPN, tlb->EPN, tlb->size,
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tlb->prot & PAGE_READ ? 'r' : '-',
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tlb->prot & PAGE_WRITE ? 'w' : '-',
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tlb->prot & PAGE_EXEC ? 'x' : '-',
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tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
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qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx
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" EPN " TARGET_FMT_lx
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" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
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(int)entry, tlb->RPN, tlb->EPN, tlb->size,
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tlb->prot & PAGE_READ ? 'r' : '-',
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tlb->prot & PAGE_WRITE ? 'w' : '-',
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tlb->prot & PAGE_EXEC ? 'x' : '-',
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tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
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}
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target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address)
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@ -816,8 +809,8 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
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target_ulong EPN, RPN, size;
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int do_flush_tlbs;
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LOG_SWTLB("%s word %d entry %d value " TARGET_FMT_lx "\n",
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__func__, word, (int)entry, value);
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qemu_log_mask(CPU_LOG_MMU, "%s word %d entry %d value " TARGET_FMT_lx "\n",
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__func__, word, (int)entry, value);
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do_flush_tlbs = 0;
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entry &= 0x3F;
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tlb = &env->tlb.tlbe[entry];
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