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riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}

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Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.

Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bin Meng 2019-09-06 09:19:58 -07:00 • committed by Palmer Dabbelt
parent 9baa9f7c9f
commit 56449d20e9
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GPG key ID: EF4CA1502CCBAB41
5 changed files with 111 additions and 114 deletions
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69
include/hw/riscv/sifive_e_prci.h Normal file
View file

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/*
* QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface
*
* Copyright (c) 2017 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_SIFIVE_E_PRCI_H
#define HW_SIFIVE_E_PRCI_H
enum {
SIFIVE_E_PRCI_HFROSCCFG = 0x0,
SIFIVE_E_PRCI_HFXOSCCFG = 0x4,
SIFIVE_E_PRCI_PLLCFG = 0x8,
SIFIVE_E_PRCI_PLLOUTDIV = 0xC
};
enum {
SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31),
SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30)
};
enum {
SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31),
SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30)
};
enum {
SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16),
SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17),
SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18),
SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31)
};
enum {
SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
};
#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
#define SIFIVE_E_PRCI(obj) \
OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI)
typedef struct SiFiveEPRCIState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion mmio;
uint32_t hfrosccfg;
uint32_t hfxosccfg;
uint32_t pllcfg;
uint32_t plloutdiv;
} SiFiveEPRCIState;
DeviceState *sifive_e_prci_create(hwaddr addr);
#endif