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hw/ppc/ppc4xx_pci: Move ppc4xx_pci.c to hw/pci-host/
ppc4xx_pci.c is moved from the target specific ppc_ss[] meson source set to pci_ss[] which is common to all targets: the object is built once. Declare PPC4XX_PCI selector in pci-host/Kconfig. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20240215105017.57748-4-philmd@linaro.org>
This commit is contained in:
parent
4d641f36e7
commit
55abb29e63
9 changed files with 12 additions and 7 deletions
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@ -53,7 +53,7 @@ config PPC440
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config PPC4XX
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bool
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select BITBANG_I2C
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select PCI
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select PPC4XX_PCI
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select PPC_UIC
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config SAM460EX
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@ -63,7 +63,6 @@ ppc_ss.add(when: 'CONFIG_PPC440', if_true: files(
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'ppc440_pcix.c', 'ppc440_uc.c'))
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ppc_ss.add(when: 'CONFIG_PPC4XX', if_true: files(
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'ppc4xx_devs.c',
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'ppc4xx_pci.c',
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'ppc4xx_sdram.c'))
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ppc_ss.add(when: 'CONFIG_SAM460EX', if_true: files('sam460ex.c'))
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# PReP
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@ -1,400 +0,0 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright IBM Corp. 2008
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*
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* Authors: Hollis Blanchard <hollisb@us.ibm.com>
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*/
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/*
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* This file implements emulation of the 32-bit PCI controller found in some
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* 4xx SoCs, such as the 440EP.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/pci-host/ppc4xx.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "sysemu/reset.h"
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#include "hw/pci/pci_device.h"
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#include "hw/pci/pci_host.h"
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#include "trace.h"
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#include "qom/object.h"
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struct PCIMasterMap {
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uint32_t la;
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uint32_t ma;
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uint32_t pcila;
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uint32_t pciha;
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};
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struct PCITargetMap {
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uint32_t ms;
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uint32_t la;
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};
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OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST)
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#define PPC4xx_PCI_NR_PMMS 3
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#define PPC4xx_PCI_NR_PTMS 2
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#define PPC4xx_PCI_NUM_DEVS 5
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struct PPC4xxPCIState {
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PCIHostState parent_obj;
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struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
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struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
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qemu_irq irq[PPC4xx_PCI_NUM_DEVS];
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MemoryRegion container;
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MemoryRegion iomem;
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};
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#define PCIC0_CFGADDR 0x0
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#define PCIC0_CFGDATA 0x4
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/*
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* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
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* PCI accesses.
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*/
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#define PCIL0_PMM0LA 0x0
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#define PCIL0_PMM0MA 0x4
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#define PCIL0_PMM0PCILA 0x8
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#define PCIL0_PMM0PCIHA 0xc
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#define PCIL0_PMM1LA 0x10
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#define PCIL0_PMM1MA 0x14
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#define PCIL0_PMM1PCILA 0x18
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#define PCIL0_PMM1PCIHA 0x1c
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#define PCIL0_PMM2LA 0x20
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#define PCIL0_PMM2MA 0x24
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#define PCIL0_PMM2PCILA 0x28
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#define PCIL0_PMM2PCIHA 0x2c
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/*
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* PCI Target Map (PTM) registers specify which PCI addresses are translated to
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* PLB accesses.
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*/
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#define PCIL0_PTM1MS 0x30
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#define PCIL0_PTM1LA 0x34
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#define PCIL0_PTM2MS 0x38
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#define PCIL0_PTM2LA 0x3c
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#define PCI_REG_BASE 0x800000
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#define PCI_REG_SIZE 0x40
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#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
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static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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struct PPC4xxPCIState *pci = opaque;
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/*
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* We ignore all target attempts at PCI configuration, effectively
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* assuming a bidirectional 1:1 mapping of PLB and PCI space.
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*/
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switch (offset) {
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case PCIL0_PMM0LA:
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pci->pmm[0].la = value;
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break;
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case PCIL0_PMM0MA:
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pci->pmm[0].ma = value;
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break;
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case PCIL0_PMM0PCIHA:
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pci->pmm[0].pciha = value;
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break;
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case PCIL0_PMM0PCILA:
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pci->pmm[0].pcila = value;
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break;
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case PCIL0_PMM1LA:
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pci->pmm[1].la = value;
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break;
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case PCIL0_PMM1MA:
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pci->pmm[1].ma = value;
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break;
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case PCIL0_PMM1PCIHA:
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pci->pmm[1].pciha = value;
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break;
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case PCIL0_PMM1PCILA:
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pci->pmm[1].pcila = value;
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break;
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case PCIL0_PMM2LA:
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pci->pmm[2].la = value;
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break;
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case PCIL0_PMM2MA:
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pci->pmm[2].ma = value;
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break;
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case PCIL0_PMM2PCIHA:
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pci->pmm[2].pciha = value;
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break;
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case PCIL0_PMM2PCILA:
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pci->pmm[2].pcila = value;
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break;
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case PCIL0_PTM1MS:
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pci->ptm[0].ms = value;
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break;
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case PCIL0_PTM1LA:
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pci->ptm[0].la = value;
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break;
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case PCIL0_PTM2MS:
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pci->ptm[1].ms = value;
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break;
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case PCIL0_PTM2LA:
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pci->ptm[1].la = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: unhandled PCI internal register 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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}
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}
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static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
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unsigned size)
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{
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struct PPC4xxPCIState *pci = opaque;
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uint32_t value;
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switch (offset) {
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case PCIL0_PMM0LA:
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value = pci->pmm[0].la;
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break;
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case PCIL0_PMM0MA:
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value = pci->pmm[0].ma;
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break;
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case PCIL0_PMM0PCIHA:
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value = pci->pmm[0].pciha;
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break;
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case PCIL0_PMM0PCILA:
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value = pci->pmm[0].pcila;
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break;
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case PCIL0_PMM1LA:
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value = pci->pmm[1].la;
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break;
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case PCIL0_PMM1MA:
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value = pci->pmm[1].ma;
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break;
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case PCIL0_PMM1PCIHA:
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value = pci->pmm[1].pciha;
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break;
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case PCIL0_PMM1PCILA:
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value = pci->pmm[1].pcila;
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break;
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case PCIL0_PMM2LA:
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value = pci->pmm[2].la;
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break;
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case PCIL0_PMM2MA:
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value = pci->pmm[2].ma;
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break;
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case PCIL0_PMM2PCIHA:
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value = pci->pmm[2].pciha;
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break;
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case PCIL0_PMM2PCILA:
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value = pci->pmm[2].pcila;
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break;
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case PCIL0_PTM1MS:
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value = pci->ptm[0].ms;
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break;
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case PCIL0_PTM1LA:
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value = pci->ptm[0].la;
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break;
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case PCIL0_PTM2MS:
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value = pci->ptm[1].ms;
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break;
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case PCIL0_PTM2LA:
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value = pci->ptm[1].la;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid PCI internal register 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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value = 0;
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}
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return value;
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}
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static const MemoryRegionOps pci_reg_ops = {
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.read = ppc4xx_pci_reg_read4,
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.write = ppc4xx_pci_reg_write4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void ppc4xx_pci_reset(void *opaque)
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{
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struct PPC4xxPCIState *pci = opaque;
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memset(pci->pmm, 0, sizeof(pci->pmm));
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memset(pci->ptm, 0, sizeof(pci->ptm));
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}
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/*
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* On Bamboo, all pins from each slot are tied to a single board IRQ.
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* This may need further refactoring for other boards.
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*/
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static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int slot = PCI_SLOT(pci_dev->devfn);
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trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot);
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return slot > 0 ? slot - 1 : PPC4xx_PCI_NUM_DEVS - 1;
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}
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static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pci_irqs = opaque;
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trace_ppc4xx_pci_set_irq(irq_num);
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assert(irq_num >= 0 && irq_num < PPC4xx_PCI_NUM_DEVS);
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qemu_set_irq(pci_irqs[irq_num], level);
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}
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static const VMStateDescription vmstate_pci_master_map = {
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.name = "pci_master_map",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(la, struct PCIMasterMap),
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VMSTATE_UINT32(ma, struct PCIMasterMap),
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VMSTATE_UINT32(pcila, struct PCIMasterMap),
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VMSTATE_UINT32(pciha, struct PCIMasterMap),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_pci_target_map = {
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.name = "pci_target_map",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(ms, struct PCITargetMap),
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VMSTATE_UINT32(la, struct PCITargetMap),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_ppc4xx_pci = {
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.name = "ppc4xx_pci",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
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vmstate_pci_master_map,
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struct PCIMasterMap),
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VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
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vmstate_pci_target_map,
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struct PCITargetMap),
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VMSTATE_END_OF_LIST()
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}
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};
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/* XXX Interrupt acknowledge cycles not supported. */
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static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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PPC4xxPCIState *s;
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PCIHostState *h;
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PCIBus *b;
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int i;
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h = PCI_HOST_BRIDGE(dev);
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s = PPC4xx_PCI_HOST(dev);
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for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
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sysbus_init_irq(sbd, &s->irq[i]);
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}
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b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq,
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ppc4xx_pci_map_irq, s->irq, get_system_memory(),
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get_system_io(), 0, ARRAY_SIZE(s->irq),
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TYPE_PCI_BUS);
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h->bus = b;
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pci_create_simple(b, 0, TYPE_PPC4xx_HOST_BRIDGE);
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/* XXX split into 2 memory regions, one for config space, one for regs */
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memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
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memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
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"pci-conf-idx", 4);
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memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
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"pci-conf-data", 4);
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memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
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"pci.reg", PCI_REG_SIZE);
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memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
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memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
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memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
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sysbus_init_mmio(sbd, &s->container);
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qemu_register_reset(ppc4xx_pci_reset, s);
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}
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static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "Host bridge";
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k->vendor_id = PCI_VENDOR_ID_IBM;
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k->device_id = PCI_DEVICE_ID_IBM_440GX;
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k->class_id = PCI_CLASS_BRIDGE_OTHER;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo ppc4xx_host_bridge_info = {
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.name = TYPE_PPC4xx_HOST_BRIDGE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = ppc4xx_host_bridge_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = ppc4xx_pcihost_realize;
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dc->vmsd = &vmstate_ppc4xx_pci;
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}
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static const TypeInfo ppc4xx_pcihost_info = {
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.name = TYPE_PPC4xx_PCI_HOST,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.instance_size = sizeof(PPC4xxPCIState),
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.class_init = ppc4xx_pcihost_class_init,
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};
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static void ppc4xx_pci_register_types(void)
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{
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type_register_static(&ppc4xx_pcihost_info);
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type_register_static(&ppc4xx_host_bridge_info);
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}
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type_init(ppc4xx_pci_register_types)
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@ -146,10 +146,6 @@ rs6000mc_size_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x"
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rs6000mc_size_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"
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rs6000mc_parity_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x"
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# ppc4xx_pci.c
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ppc4xx_pci_map_irq(int32_t devfn, int irq_num, int slot) "devfn 0x%x irq %d -> %d"
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ppc4xx_pci_set_irq(int irq_num) "PCI irq %d"
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# ppc440_pcix.c
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ppc440_pcix_map_irq(int32_t devfn, int irq_num, int slot) "devfn 0x%x irq %d -> %d"
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ppc440_pcix_set_irq(int irq_num) "PCI irq %d"
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