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hw/misc/aspeed_hace: Add trace-events for better debugging

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Introduced "trace_aspeed_hace_hash_addr", "trace_aspeed_hace_hash_sg",
"trace_aspeed_hace_read", "trace_aspeed_hace_hash_execute_acc_mode",
and "trace_aspeed_hace_write" trace events.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-16-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-05-15 16:09:47 +08:00 • committed by Cédric Le Goater
parent 7e65aa39b3
commit 555167a8fd
2 changed files with 17 additions and 0 deletions
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10
hw/misc/aspeed_hace.c
View file

@ -18,6 +18,7 @@
#include "crypto/hash.h"
#include "hw/qdev-properties.h"
#include "hw/irq.h"
#include "trace.h"
#define R_CRYPT_CMD (0x10 / 4)
@ -170,6 +171,7 @@ static int hash_prepare_direct_iov(AspeedHACEState *s, struct iovec *iov,
plen = s->regs[R_HASH_SRC_LEN];
src = hash_get_source_addr(s);
trace_aspeed_hace_hash_addr("src", src);
haddr = address_space_map(&s->dram_as, src, &plen, false,
MEMTXATTRS_UNSPECIFIED);
if (haddr == NULL) {
@ -227,6 +229,7 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, struct iovec *iov,
sg_addr = address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SIZE,
MEMTXATTRS_UNSPECIFIED, NULL);
sg_addr &= SG_LIST_ADDR_MASK;
trace_aspeed_hace_hash_sg(iov_idx, src, sg_addr, len);
/*
* To maintain compatibility with older SoCs such as the AST2600,
* the AST2700 HW automatically set bit 34 of the 64-bit sg_addr.
@ -290,6 +293,7 @@ static void hash_write_digest_and_unmap_iov(AspeedHACEState *s,
uint64_t digest_addr = 0;
digest_addr = hash_get_digest_addr(s);
trace_aspeed_hace_hash_addr("digest", digest_addr);
if (address_space_write(&s->dram_as, digest_addr,
MEMTXATTRS_UNSPECIFIED,
digest_buf, digest_len)) {
@ -332,6 +336,8 @@ static void hash_execute_acc_mode(AspeedHACEState *s, int algo,
Error *local_err = NULL;
size_t digest_len = 0;
trace_aspeed_hace_hash_execute_acc_mode(final_request);
if (s->hash_ctx == NULL) {
s->hash_ctx = qcrypto_hash_new(algo, &local_err);
if (s->hash_ctx == NULL) {
@ -403,6 +409,8 @@ static uint64_t aspeed_hace_read(void *opaque, hwaddr addr, unsigned int size)
addr >>= 2;
trace_aspeed_hace_read(addr << 2, s->regs[addr]);
return s->regs[addr];
}
@ -414,6 +422,8 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
addr >>= 2;
trace_aspeed_hace_write(addr << 2, data);
switch (addr) {
case R_STATUS:
if (data & HASH_IRQ) {

7
hw/misc/trace-events
View file

@ -302,6 +302,13 @@ aspeed_peci_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%"
aspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRIx32 " status 0x%" PRIx32
# aspeed_hace.c
aspeed_hace_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_hace_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_hace_hash_sg(int index, uint64_t list_addr, uint64_t buf_addr, uint32_t len) "%d: list_addr 0x%" PRIx64 " buf_addr 0x%" PRIx64 " len 0x%" PRIx32
aspeed_hace_hash_addr(const char *s, uint64_t addr) "%s: 0x%" PRIx64
aspeed_hace_hash_execute_acc_mode(bool final_request) "final request: %d"
# bcm2835_property.c
bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu"