mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-08 18:23:57 -06:00
MIPS patches queue
- Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition - Various Toshiba TX79 opcodes implemented - Rewrite UHI errno_mips() using switch statement - Few fixes and improvements in the SONIC model (dp8393x) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmDrXtEACgkQ4+MsLN6t wN6wEQ//S+E65VWQAZFpyVBQYMoGeMeJUy5ABA7ec7uI1Zvsr1Xq/skw7Z/4ys29 Lfdg5dqxyL+Wj5g/LjE5+Cfql59DjP3HsK8D0DyYBtwMju8iCFh+TYPOAoUQ3Qhl 1tsOY32aaE1Fi7EvmpEJs91LbwpOAxdoCRRy5ScoZ54+XPaG8xA318dYVgvc8tpc W+vdUZfZ2nn/8SF3vEBi8KkcrNtW36h4WzjTN+aA6I5O9TZ66I0lBuix4VX5yCKl 4zRRYOSepcWvU23FNN4H4lJCwMOqb5lcul7Shfq78KRqX1g0WUhIrfDBR19wqypj YF9llgwZXXnU+R9aOrtQpfBh4eDjySaZmOyaIg3oR+BZWAYk6Lvf7fL8hSW0HhWX 8k2uic9uMoQlcs434Q7uzVwoMEh5aPl9GHiUOxBd7pM+P6xsB8S7vLzdmd23npuy r/6ALnoWLzPrN+y6tHtqu70rpyE+klh+S09jwNJZSzECGLG3nkACSOdwv7TKyPki gJfwIYdtC+JEVIr48GnvbzsTV+aBG5TItHuQpaJciD000P4m0dYXpDoaO7cxH4Qt AAUtYkvEYPE0ktWvTt2jQDn8Ma1SdKdtfWKRcWKaMiBM44GoRqyWaUQhjGLwto6v ocY0/JplqdcKdPIedFAw2ednlDqeJpRMs0ikv1yhgtts1nQ8MF0= =t1ur -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/philmd/tags/mips-20210711' into staging MIPS patches queue - Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition - Various Toshiba TX79 opcodes implemented - Rewrite UHI errno_mips() using switch statement - Few fixes and improvements in the SONIC model (dp8393x) # gpg: Signature made Sun 11 Jul 2021 22:12:49 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/mips-20210711: dp8393x: don't force 32-bit register access dp8393x: Rewrite dp8393x_get() / dp8393x_put() dp8393x: Store CAM registers as 16-bit dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition dp8393x: Replace address_space_rw(is_write=1) by address_space_write() dp8393x: fix CAM descriptor entry index target/mips: Rewrite UHI errno_mips() using switch statement target/mips/tx79: Introduce SQ opcode (Store Quadword) target/mips/tx79: Introduce LQ opcode (Load Quadword) target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words) target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word) target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than) target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal) target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower) target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word) target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition hw/pci-host: Rename Raven ASIC PCI bridge as raven.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
552fda48e0
10 changed files with 526 additions and 157 deletions
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@ -74,25 +74,19 @@ enum UHIOpenFlags {
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UHIOpen_EXCL = 0x800
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};
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/* Errno values taken from asm-mips/errno.h */
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static const uint16_t host_to_mips_errno[] = {
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[ENAMETOOLONG] = 78,
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static int errno_mips(int host_errno)
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{
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/* Errno values taken from asm-mips/errno.h */
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switch (host_errno) {
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case 0: return 0;
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case ENAMETOOLONG: return 78;
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#ifdef EOVERFLOW
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[EOVERFLOW] = 79,
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case EOVERFLOW: return 79;
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#endif
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#ifdef ELOOP
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[ELOOP] = 90,
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case ELOOP: return 90;
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#endif
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};
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static int errno_mips(int err)
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{
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if (err < 0 || err >= ARRAY_SIZE(host_to_mips_errno)) {
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return EINVAL;
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} else if (host_to_mips_errno[err]) {
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return host_to_mips_errno[err];
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} else {
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return err;
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default: return EINVAL;
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}
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}
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@ -1179,7 +1179,6 @@ enum {
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enum {
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MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
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MMI_OPC_LQ = 0x1E << 26, /* Same as OPC_MSA */
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MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
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};
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@ -15166,11 +15165,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
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{
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gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */
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}
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static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
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{
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gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
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@ -16069,14 +16063,8 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
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gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
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}
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break;
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case OPC_MDMX: /* MMI_OPC_LQ */
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if (ctx->insn_flags & INSN_R5900) {
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#if defined(TARGET_MIPS64)
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gen_mmi_lq(env, ctx);
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#endif
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} else {
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/* MDMX: Not implemented. */
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}
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case OPC_MDMX:
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/* MDMX: Not implemented. */
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break;
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case OPC_PCREL:
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check_insn(ctx, ISA_MIPS_R6);
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@ -13,6 +13,8 @@
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&rtype rs rt rd sa
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&itype base rt offset
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###########################################################################
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# Named instruction formats. These are generally used to
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# reduce the amount of duplication between instruction patterns.
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@ -22,6 +24,8 @@
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@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0
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@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0
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@ldst ...... base:5 rt:5 offset:16 &itype
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###########################################################################
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MFHI1 011100 0000000000 ..... 00000 010000 @rd
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@ -29,11 +33,41 @@ MTHI1 011100 ..... 0000000000 00000 010001 @rs
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MFLO1 011100 0000000000 ..... 00000 010010 @rd
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MTLO1 011100 ..... 0000000000 00000 010011 @rs
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# MMI0
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PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd
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PCGTW 011100 ..... ..... ..... 00010 001000 @rs_rt_rd
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PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd
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PCGTH 011100 ..... ..... ..... 00110 001000 @rs_rt_rd
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PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd
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PCGTB 011100 ..... ..... ..... 01010 001000 @rs_rt_rd
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PEXTLW 011100 ..... ..... ..... 10010 001000 @rs_rt_rd
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PPACW 011100 ..... ..... ..... 10011 001000 @rs_rt_rd
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PEXTLH 011100 ..... ..... ..... 10110 001000 @rs_rt_rd
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PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd
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# MMI1
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PCEQW 011100 ..... ..... ..... 00010 101000 @rs_rt_rd
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PCEQH 011100 ..... ..... ..... 00110 101000 @rs_rt_rd
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PCEQB 011100 ..... ..... ..... 01010 101000 @rs_rt_rd
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PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd
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# MMI2
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PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd
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PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd
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PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd
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PROT3W 011100 00000 ..... ..... 11111 001001 @rt_rd
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# MMI3
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PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd
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POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd
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PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd
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PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd
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# SPECIAL
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LQ 011110 ..... ..... ................ @ldst
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SQ 011111 ..... ..... ................ @ldst
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@ -2,12 +2,14 @@
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* Toshiba TX79-specific instructions translation routines
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*
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* Copyright (c) 2018 Fredrik Noring
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* Copyright (c) 2021 Philippe Mathieu-Daudé
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "tcg/tcg-op.h"
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#include "tcg/tcg-op-gvec.h"
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#include "exec/helper-gen.h"
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#include "translate.h"
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@ -114,6 +116,53 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
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* PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
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*/
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static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a,
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void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64))
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{
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TCGv_i64 ax, bx;
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if (a->rd == 0) {
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/* nop */
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return true;
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}
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ax = tcg_temp_new_i64();
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bx = tcg_temp_new_i64();
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/* Lower half */
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gen_load_gpr(ax, a->rs);
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gen_load_gpr(bx, a->rt);
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gen_logic_i64(cpu_gpr[a->rd], ax, bx);
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/* Upper half */
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gen_load_gpr_hi(ax, a->rs);
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gen_load_gpr_hi(bx, a->rt);
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gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx);
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tcg_temp_free(bx);
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tcg_temp_free(ax);
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return true;
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}
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/* Parallel Subtract Byte */
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static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_arith(ctx, a, tcg_gen_vec_sub8_i64);
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}
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/* Parallel Subtract Halfword */
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static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_arith(ctx, a, tcg_gen_vec_sub16_i64);
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}
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/* Parallel Subtract Word */
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static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_arith(ctx, a, tcg_gen_vec_sub32_i64);
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}
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/*
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* Min/Max (4 instructions)
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* ------------------------
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@ -139,6 +188,30 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
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* PNOR rd, rs, rt Parallel NOR
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*/
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/* Parallel And */
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static bool trans_PAND(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_arith(ctx, a, tcg_gen_and_i64);
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}
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/* Parallel Or */
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static bool trans_POR(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_arith(ctx, a, tcg_gen_or_i64);
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}
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/* Parallel Exclusive Or */
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static bool trans_PXOR(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_arith(ctx, a, tcg_gen_xor_i64);
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}
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/* Parallel Not Or */
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static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_arith(ctx, a, tcg_gen_nor_i64);
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}
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/*
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* Shift (9 instructions)
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* ----------------------
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@ -164,6 +237,90 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
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* PCEQW rd, rs, rt Parallel Compare for Equal Word
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*/
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static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a,
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TCGCond cond, unsigned wlen)
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{
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TCGv_i64 c0, c1, ax, bx, t0, t1, t2;
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if (a->rd == 0) {
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/* nop */
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return true;
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}
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c0 = tcg_const_tl(0);
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c1 = tcg_const_tl(0xffffffff);
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ax = tcg_temp_new_i64();
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bx = tcg_temp_new_i64();
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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t2 = tcg_temp_new_i64();
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/* Lower half */
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gen_load_gpr(ax, a->rs);
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gen_load_gpr(bx, a->rt);
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for (int i = 0; i < (64 / wlen); i++) {
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tcg_gen_sextract_i64(t0, ax, wlen * i, wlen);
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tcg_gen_sextract_i64(t1, bx, wlen * i, wlen);
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tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0);
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tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen);
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}
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/* Upper half */
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gen_load_gpr_hi(ax, a->rs);
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gen_load_gpr_hi(bx, a->rt);
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for (int i = 0; i < (64 / wlen); i++) {
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tcg_gen_sextract_i64(t0, ax, wlen * i, wlen);
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tcg_gen_sextract_i64(t1, bx, wlen * i, wlen);
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tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0);
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tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen);
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}
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tcg_temp_free(t2);
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tcg_temp_free(t1);
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tcg_temp_free(t0);
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tcg_temp_free(bx);
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tcg_temp_free(ax);
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tcg_temp_free(c1);
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tcg_temp_free(c0);
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return true;
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}
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/* Parallel Compare for Greater Than Byte */
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static bool trans_PCGTB(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_compare(ctx, a, TCG_COND_GE, 8);
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}
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/* Parallel Compare for Equal Byte */
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static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8);
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}
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/* Parallel Compare for Greater Than Halfword */
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static bool trans_PCGTH(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_compare(ctx, a, TCG_COND_GE, 16);
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}
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/* Parallel Compare for Equal Halfword */
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static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16);
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}
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|
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/* Parallel Compare for Greater Than Word */
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static bool trans_PCGTW(DisasContext *ctx, arg_rtype *a)
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{
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return trans_parallel_compare(ctx, a, TCG_COND_GE, 32);
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}
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/* Parallel Compare for Equal Word */
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static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
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{
|
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return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32);
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}
|
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|
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/*
|
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* LZC (1 instruction)
|
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* -------------------
|
||||
|
|
@ -177,6 +334,68 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
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* SQ rt, offset(base) Store Quadword
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*/
|
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|
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static bool trans_LQ(DisasContext *ctx, arg_itype *a)
|
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{
|
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TCGv_i64 t0;
|
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TCGv addr;
|
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|
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if (a->rt == 0) {
|
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/* nop */
|
||||
return true;
|
||||
}
|
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|
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t0 = tcg_temp_new_i64();
|
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addr = tcg_temp_new();
|
||||
|
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gen_base_offset_addr(ctx, addr, a->base, a->offset);
|
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/*
|
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* Clear least-significant four bits of the effective
|
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* address, effectively creating an aligned address.
|
||||
*/
|
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tcg_gen_andi_tl(addr, addr, ~0xf);
|
||||
|
||||
/* Lower half */
|
||||
tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ);
|
||||
gen_store_gpr(t0, a->rt);
|
||||
|
||||
/* Upper half */
|
||||
tcg_gen_addi_i64(addr, addr, 8);
|
||||
tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ);
|
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gen_store_gpr_hi(t0, a->rt);
|
||||
|
||||
tcg_temp_free(t0);
|
||||
tcg_temp_free(addr);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_SQ(DisasContext *ctx, arg_itype *a)
|
||||
{
|
||||
TCGv_i64 t0 = tcg_temp_new_i64();
|
||||
TCGv addr = tcg_temp_new();
|
||||
|
||||
gen_base_offset_addr(ctx, addr, a->base, a->offset);
|
||||
/*
|
||||
* Clear least-significant four bits of the effective
|
||||
* address, effectively creating an aligned address.
|
||||
*/
|
||||
tcg_gen_andi_tl(addr, addr, ~0xf);
|
||||
|
||||
/* Lower half */
|
||||
gen_load_gpr(t0, a->rt);
|
||||
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ);
|
||||
|
||||
/* Upper half */
|
||||
tcg_gen_addi_i64(addr, addr, 8);
|
||||
gen_load_gpr_hi(t0, a->rt);
|
||||
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ);
|
||||
|
||||
tcg_temp_free(addr);
|
||||
tcg_temp_free(t0);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Multiply and Divide (19 instructions)
|
||||
* -------------------------------------
|
||||
|
|
@ -217,6 +436,141 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
|
|||
* PEXTLW rd, rs, rt Parallel Extend Lower from Word
|
||||
*/
|
||||
|
||||
/* Parallel Pack to Word */
|
||||
static bool trans_PPACW(DisasContext *ctx, arg_rtype *a)
|
||||
{
|
||||
TCGv_i64 a0, b0, t0;
|
||||
|
||||
if (a->rd == 0) {
|
||||
/* nop */
|
||||
return true;
|
||||
}
|
||||
|
||||
a0 = tcg_temp_new_i64();
|
||||
b0 = tcg_temp_new_i64();
|
||||
t0 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_gpr(a0, a->rs);
|
||||
gen_load_gpr(b0, a->rt);
|
||||
|
||||
gen_load_gpr_hi(t0, a->rt); /* b1 */
|
||||
tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32);
|
||||
|
||||
gen_load_gpr_hi(t0, a->rs); /* a1 */
|
||||
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32);
|
||||
|
||||
tcg_temp_free(t0);
|
||||
tcg_temp_free(b0);
|
||||
tcg_temp_free(a0);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 a, TCGv_i64 b)
|
||||
{
|
||||
tcg_gen_deposit_i64(dl, b, a, 32, 32);
|
||||
tcg_gen_shri_i64(b, b, 32);
|
||||
tcg_gen_deposit_i64(dh, a, b, 0, 32);
|
||||
}
|
||||
|
||||
static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen)
|
||||
{
|
||||
TCGv_i64 ax, bx;
|
||||
|
||||
if (a->rd == 0) {
|
||||
/* nop */
|
||||
return true;
|
||||
}
|
||||
|
||||
ax = tcg_temp_new_i64();
|
||||
bx = tcg_temp_new_i64();
|
||||
|
||||
gen_load_gpr(ax, a->rs);
|
||||
gen_load_gpr(bx, a->rt);
|
||||
|
||||
/* Lower half */
|
||||
for (int i = 0; i < 64 / (2 * wlen); i++) {
|
||||
tcg_gen_deposit_i64(cpu_gpr[a->rd],
|
||||
cpu_gpr[a->rd], bx, 2 * wlen * i, wlen);
|
||||
tcg_gen_deposit_i64(cpu_gpr[a->rd],
|
||||
cpu_gpr[a->rd], ax, 2 * wlen * i + wlen, wlen);
|
||||
tcg_gen_shri_i64(bx, bx, wlen);
|
||||
tcg_gen_shri_i64(ax, ax, wlen);
|
||||
}
|
||||
/* Upper half */
|
||||
for (int i = 0; i < 64 / (2 * wlen); i++) {
|
||||
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
|
||||
cpu_gpr_hi[a->rd], bx, 2 * wlen * i, wlen);
|
||||
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
|
||||
cpu_gpr_hi[a->rd], ax, 2 * wlen * i + wlen, wlen);
|
||||
tcg_gen_shri_i64(bx, bx, wlen);
|
||||
tcg_gen_shri_i64(ax, ax, wlen);
|
||||
}
|
||||
|
||||
tcg_temp_free(bx);
|
||||
tcg_temp_free(ax);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Parallel Extend Lower from Byte */
|
||||
static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a)
|
||||
{
|
||||
return trans_PEXTLx(ctx, a, 8);
|
||||
}
|
||||
|
||||
/* Parallel Extend Lower from Halfword */
|
||||
static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a)
|
||||
{
|
||||
return trans_PEXTLx(ctx, a, 16);
|
||||
}
|
||||
|
||||
/* Parallel Extend Lower from Word */
|
||||
static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a)
|
||||
{
|
||||
TCGv_i64 ax, bx;
|
||||
|
||||
if (a->rd == 0) {
|
||||
/* nop */
|
||||
return true;
|
||||
}
|
||||
|
||||
ax = tcg_temp_new_i64();
|
||||
bx = tcg_temp_new_i64();
|
||||
|
||||
gen_load_gpr(ax, a->rs);
|
||||
gen_load_gpr(bx, a->rt);
|
||||
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
|
||||
|
||||
tcg_temp_free(bx);
|
||||
tcg_temp_free(ax);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Parallel Extend Upper from Word */
|
||||
static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
|
||||
{
|
||||
TCGv_i64 ax, bx;
|
||||
|
||||
if (a->rd == 0) {
|
||||
/* nop */
|
||||
return true;
|
||||
}
|
||||
|
||||
ax = tcg_temp_new_i64();
|
||||
bx = tcg_temp_new_i64();
|
||||
|
||||
gen_load_gpr_hi(ax, a->rs);
|
||||
gen_load_gpr_hi(bx, a->rt);
|
||||
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
|
||||
|
||||
tcg_temp_free(bx);
|
||||
tcg_temp_free(ax);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Others (16 instructions)
|
||||
* ------------------------
|
||||
|
|
@ -301,3 +655,31 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
|
|||
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Parallel Rotate 3 Words Left */
|
||||
static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a)
|
||||
{
|
||||
TCGv_i64 ax;
|
||||
|
||||
if (a->rd == 0) {
|
||||
/* nop */
|
||||
return true;
|
||||
}
|
||||
if (a->rt == 0) {
|
||||
tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
|
||||
tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
|
||||
return true;
|
||||
}
|
||||
|
||||
ax = tcg_temp_new_i64();
|
||||
|
||||
tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]);
|
||||
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, cpu_gpr[a->rt], 0, 32);
|
||||
|
||||
tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32);
|
||||
tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32);
|
||||
|
||||
tcg_temp_free(ax);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue