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target/riscv: Add support for the 32-bit MSTATUSH CSR

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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Alistair Francis 2020-01-31 17:03:05 -08:00 • committed by Palmer Dabbelt
parent 3067553993
commit 551fa7e8a6
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6 changed files with 62 additions and 0 deletions
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10
target/riscv/cpu.h
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@ -127,6 +127,10 @@ struct CPURISCVState {
target_ulong mip;
#ifdef TARGET_RISCV32
target_ulong mstatush;
#endif
uint32_t miclaim;
target_ulong mie;
@ -164,6 +168,9 @@ struct CPURISCVState {
target_ulong vscause;
target_ulong vstval;
target_ulong vsatp;
#ifdef TARGET_RISCV32
target_ulong vsstatush;
#endif
target_ulong mtval2;
target_ulong mtinst;
@ -176,6 +183,9 @@ struct CPURISCVState {
target_ulong stval_hs;
target_ulong satp_hs;
target_ulong mstatus_hs;
#ifdef TARGET_RISCV32
target_ulong mstatush_hs;
#endif
target_ulong scounteren;
target_ulong mcounteren;