motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 16:23:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC

Browse source 
The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:

- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A1 SSP SoC
- Implement initialization and realization functions
- Add support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO

The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt controller.

Difference from AST2700:

    - AST2700
      - Support GICINT128 to GICINT136 in INTC
      - The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
          Bit 0 -> GIC 192
          Bit 1 -> GIC 193
          Bit 2 -> GIC 194
          Bit 3 -> GIC 195
          Bit 4 -> GIC 196

    - AST2700-ssp
      - Support SSPINT128 to SSPINT136 in INTC
      - The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
          Bit 0 -> SSPINT 160
          Bit 1 -> SSPINT 161
          Bit 2 -> SSPINT 162
          Bit 3 -> SSPINT 163
          Bit 4 -> SSPINT 164

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I924bf1a657f1e83f9e16d6673713f4a06ecdb496
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250502103449.3091642-6-steven_lee@aspeedtech.com
[ clg: removed local 'Error* err' in aspeed_soc_ast27x0ssp_realize() ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Steven Lee 2025-05-02 18:34:41 +08:00 • committed by Cédric Le Goater
parent c528f10dce
commit 541da2604f
3 changed files with 309 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

14
include/hw/arm/aspeed_soc.h
View file

@ -146,6 +146,18 @@ struct Aspeed10x0SoCState {
ARMv7MState armv7m;
};
struct Aspeed27x0SSPSoCState {
AspeedSoCState parent;
AspeedINTCState intc[2];
UnimplementedDeviceState ipc[2];
UnimplementedDeviceState scuio;
ARMv7MState armv7m;
};
#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
@ -259,6 +271,8 @@ enum {
ASPEED_DEV_SLIIO,
ASPEED_GIC_DIST,
ASPEED_GIC_REDIST,
ASPEED_DEV_IPC0,
ASPEED_DEV_IPC1,
};
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);