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target/riscv: Add J-extension into RISC-V

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Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211025173609.2724490-2-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alexey Baturo 2021-10-25 20:36:02 +03:00 • committed by Alistair Francis
parent 9b144ed444
commit 53dcea58b8
1 changed files with 2 additions and 0 deletions
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2
target/riscv/cpu.h
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@ -65,6 +65,7 @@
#define RVS RV('S') #define RVS RV('S')
#define RVU RV('U') #define RVU RV('U')
#define RVH RV('H') #define RVH RV('H')
#define RVJ RV('J')
/* S extension denotes that Supervisor mode exists, however it is possible /* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there to have a core that support S mode but does not have an MMU and there
@ -291,6 +292,7 @@ struct RISCVCPU {
bool ext_s; bool ext_s;
bool ext_u; bool ext_u;
bool ext_h; bool ext_h;
bool ext_j;
bool ext_v; bool ext_v;
bool ext_zba; bool ext_zba;
bool ext_zbb; bool ext_zbb;