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linux-headers: update against 5.10-rc1
commit 3650b228f83adda7e5ee532e2b90429c03f7b9ec
Signed-off-by: Matthew Rosato <mjrosato@linux.ibm.com>
[aw: drop pvrdma_ring.h changes to avoid revert of d73415a315 ("qemu/atomic.h: rename atomic_ to qatomic_")]
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
This commit is contained in:
Matthew Rosato
Alex Williamson
parent
84567ea763
commit
53ba2eee52
28 changed files with 294 additions and 16 deletions
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@ -1617,6 +1617,8 @@ enum ethtool_link_mode_bit_indices {
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ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,
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ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88,
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ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,
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ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
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ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
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/* must be last entry */
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__ETHTOOL_LINK_MODE_MASK_NBITS
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};
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@ -172,6 +172,9 @@
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* - add FUSE_WRITE_KILL_PRIV flag
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* - add FUSE_SETUPMAPPING and FUSE_REMOVEMAPPING
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* - add map_alignment to fuse_init_out, add FUSE_MAP_ALIGNMENT flag
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*
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* 7.32
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* - add flags to fuse_attr, add FUSE_ATTR_SUBMOUNT, add FUSE_SUBMOUNTS
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*/
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#ifndef _LINUX_FUSE_H
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@ -203,7 +206,7 @@
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#define FUSE_KERNEL_VERSION 7
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/** Minor version number of this interface */
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#define FUSE_KERNEL_MINOR_VERSION 31
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#define FUSE_KERNEL_MINOR_VERSION 32
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/** The node ID of the root inode */
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#define FUSE_ROOT_ID 1
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@ -227,7 +230,7 @@ struct fuse_attr {
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uint32_t gid;
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uint32_t rdev;
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uint32_t blksize;
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uint32_t padding;
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uint32_t flags;
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};
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struct fuse_kstatfs {
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@ -309,7 +312,10 @@ struct fuse_file_lock {
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* FUSE_CACHE_SYMLINKS: cache READLINK responses
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* FUSE_NO_OPENDIR_SUPPORT: kernel supports zero-message opendir
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* FUSE_EXPLICIT_INVAL_DATA: only invalidate cached pages on explicit request
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* FUSE_MAP_ALIGNMENT: map_alignment field is valid
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* FUSE_MAP_ALIGNMENT: init_out.map_alignment contains log2(byte alignment) for
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* foffset and moffset fields in struct
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* fuse_setupmapping_out and fuse_removemapping_one.
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* FUSE_SUBMOUNTS: kernel supports auto-mounting directory submounts
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*/
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#define FUSE_ASYNC_READ (1 << 0)
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#define FUSE_POSIX_LOCKS (1 << 1)
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@ -338,6 +344,7 @@ struct fuse_file_lock {
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#define FUSE_NO_OPENDIR_SUPPORT (1 << 24)
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#define FUSE_EXPLICIT_INVAL_DATA (1 << 25)
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#define FUSE_MAP_ALIGNMENT (1 << 26)
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#define FUSE_SUBMOUNTS (1 << 27)
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/**
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* CUSE INIT request/reply flags
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@ -413,6 +420,13 @@ struct fuse_file_lock {
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*/
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#define FUSE_FSYNC_FDATASYNC (1 << 0)
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/**
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* fuse_attr flags
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*
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* FUSE_ATTR_SUBMOUNT: Object is a submount root
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*/
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#define FUSE_ATTR_SUBMOUNT (1 << 0)
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enum fuse_opcode {
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FUSE_LOOKUP = 1,
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FUSE_FORGET = 2, /* no reply */
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@ -888,4 +902,34 @@ struct fuse_copy_file_range_in {
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uint64_t flags;
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};
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#define FUSE_SETUPMAPPING_FLAG_WRITE (1ull << 0)
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#define FUSE_SETUPMAPPING_FLAG_READ (1ull << 1)
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struct fuse_setupmapping_in {
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/* An already open handle */
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uint64_t fh;
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/* Offset into the file to start the mapping */
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uint64_t foffset;
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/* Length of mapping required */
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uint64_t len;
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/* Flags, FUSE_SETUPMAPPING_FLAG_* */
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uint64_t flags;
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/* Offset in Memory Window */
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uint64_t moffset;
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};
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struct fuse_removemapping_in {
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/* number of fuse_removemapping_one follows */
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uint32_t count;
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};
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struct fuse_removemapping_one {
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/* Offset into the dax window start the unmapping */
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uint64_t moffset;
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/* Length of mapping required */
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uint64_t len;
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};
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#define FUSE_REMOVEMAPPING_MAX_ENTRY \
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(PAGE_SIZE / sizeof(struct fuse_removemapping_one))
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#endif /* _LINUX_FUSE_H */
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@ -515,6 +515,9 @@
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#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */
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#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */
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#define KEY_IMAGES 0x1ba /* AL Image Browser */
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#define KEY_NOTIFICATION_CENTER 0x1bc /* Show/hide the notification center */
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#define KEY_PICKUP_PHONE 0x1bd /* Answer incoming call */
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#define KEY_HANGUP_PHONE 0x1be /* Decline incoming call */
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#define KEY_DEL_EOL 0x1c0
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#define KEY_DEL_EOS 0x1c1
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@ -542,6 +545,7 @@
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#define KEY_FN_F 0x1e2
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#define KEY_FN_S 0x1e3
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#define KEY_FN_B 0x1e4
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#define KEY_FN_RIGHT_SHIFT 0x1e5
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#define KEY_BRL_DOT1 0x1f1
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#define KEY_BRL_DOT2 0x1f2
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@ -76,6 +76,7 @@
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#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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#define PCI_HEADER_TYPE 0x0e /* 8 bits */
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#define PCI_HEADER_TYPE_MASK 0x7f
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#define PCI_HEADER_TYPE_NORMAL 0
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#define PCI_HEADER_TYPE_BRIDGE 1
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#define PCI_HEADER_TYPE_CARDBUS 2
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@ -246,7 +247,7 @@
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#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
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#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
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#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
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#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
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#define PCI_PM_CAP_PME_D3hot 0x4000 /* PME# from D3 (hot) */
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#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
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#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */
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#define PCI_PM_CTRL 4 /* PM control and status register */
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@ -532,6 +533,8 @@
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#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
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#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
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#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
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#define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
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#define PCI_EXP_LNKCAP_ASPM_L1 0x00000800 /* ASPM L1 Support */
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#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
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#define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */
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#define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* Clock Power Management */
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@ -1056,6 +1059,7 @@
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#define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */
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#define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */
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#define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */
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#define PCI_L1SS_CTL1_L1_2_MASK 0x00000005
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#define PCI_L1SS_CTL1_L1SS_MASK 0x0000000f
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#define PCI_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 /* Common_Mode_Restore_Time */
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#define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */
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@ -16,4 +16,7 @@ struct virtio_fs_config {
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uint32_t num_request_queues;
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} QEMU_PACKED;
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/* For the id field in virtio_pci_shm_cap */
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#define VIRTIO_FS_SHMCAP_ID_CACHE 0
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#endif /* _LINUX_VIRTIO_FS_H */
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@ -50,6 +50,10 @@
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* VIRTIO_GPU_CMD_GET_EDID
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*/
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#define VIRTIO_GPU_F_EDID 1
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/*
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* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID
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*/
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#define VIRTIO_GPU_F_RESOURCE_UUID 2
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enum virtio_gpu_ctrl_type {
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VIRTIO_GPU_UNDEFINED = 0,
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@ -66,6 +70,7 @@ enum virtio_gpu_ctrl_type {
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VIRTIO_GPU_CMD_GET_CAPSET_INFO,
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VIRTIO_GPU_CMD_GET_CAPSET,
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VIRTIO_GPU_CMD_GET_EDID,
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VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
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/* 3d commands */
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VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
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@ -87,6 +92,7 @@ enum virtio_gpu_ctrl_type {
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VIRTIO_GPU_RESP_OK_CAPSET_INFO,
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VIRTIO_GPU_RESP_OK_CAPSET,
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VIRTIO_GPU_RESP_OK_EDID,
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VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
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/* error responses */
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VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
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@ -340,4 +346,17 @@ enum virtio_gpu_formats {
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VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
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};
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/* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */
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struct virtio_gpu_resource_assign_uuid {
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struct virtio_gpu_ctrl_hdr hdr;
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uint32_t resource_id;
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uint32_t padding;
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};
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/* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */
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struct virtio_gpu_resp_resource_uuid {
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struct virtio_gpu_ctrl_hdr hdr;
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uint8_t uuid[16];
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};
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#endif
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@ -122,6 +122,17 @@
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#define VIRTIO_MMIO_QUEUE_USED_LOW 0x0a0
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#define VIRTIO_MMIO_QUEUE_USED_HIGH 0x0a4
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/* Shared memory region id */
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#define VIRTIO_MMIO_SHM_SEL 0x0ac
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/* Shared memory region length, 64 bits in two halves */
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#define VIRTIO_MMIO_SHM_LEN_LOW 0x0b0
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#define VIRTIO_MMIO_SHM_LEN_HIGH 0x0b4
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/* Shared memory region base address, 64 bits in two halves */
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#define VIRTIO_MMIO_SHM_BASE_LOW 0x0b8
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#define VIRTIO_MMIO_SHM_BASE_HIGH 0x0bc
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/* Configuration atomicity value */
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#define VIRTIO_MMIO_CONFIG_GENERATION 0x0fc
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@ -113,6 +113,8 @@
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#define VIRTIO_PCI_CAP_DEVICE_CFG 4
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/* PCI configuration access */
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#define VIRTIO_PCI_CAP_PCI_CFG 5
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/* Additional shared memory capability */
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#define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8
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/* This is the PCI capability header: */
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struct virtio_pci_cap {
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@ -121,11 +123,18 @@ struct virtio_pci_cap {
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uint8_t cap_len; /* Generic PCI field: capability length */
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uint8_t cfg_type; /* Identifies the structure. */
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uint8_t bar; /* Where to find it. */
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uint8_t padding[3]; /* Pad to full dword. */
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uint8_t id; /* Multiple capabilities of the same type */
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uint8_t padding[2]; /* Pad to full dword. */
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uint32_t offset; /* Offset within bar. */
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uint32_t length; /* Length of the structure, in bytes. */
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};
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struct virtio_pci_cap64 {
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struct virtio_pci_cap cap;
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uint32_t offset_hi; /* Most sig 32 bits of offset */
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uint32_t length_hi; /* Most sig 32 bits of length */
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};
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struct virtio_pci_notify_cap {
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struct virtio_pci_cap cap;
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uint32_t notify_off_multiplier; /* Multiplier for queue_notify_off. */
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