motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-08 10:13:56 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

char: use qemu_chr_fe* functions with CharBackend argument

Browse source 
This also switches from qemu_chr_add_handlers() to
qemu_chr_fe_set_handlers(). Note that qemu_chr_fe_set_handlers() now
takes the focus when fe_open (qemu_chr_add_handlers() did take the
focus)

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20161022095318.17775-16-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Marc-André Lureau 2016-10-22 12:52:55 +03:00 • committed by Paolo Bonzini
parent fbf3cc3a67
commit 5345fdb446
47 changed files with 437 additions and 409 deletions
Download patch file Download diff file Expand all files Collapse all files

8
hw/char/bcm2835_aux.c
View file

@ -80,7 +80,7 @@ static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size)
}
}
if (s->chr.chr) {
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
}
bcm2835_aux_update(s);
return c;
@ -171,7 +171,7 @@ static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value,
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
break;
@ -283,8 +283,8 @@ static void bcm2835_aux_realize(DeviceState *dev, Error **errp)
BCM2835AuxState *s = BCM2835_AUX(dev);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, bcm2835_aux_can_receive,
bcm2835_aux_receive, NULL, s);
qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,
bcm2835_aux_receive, NULL, s, NULL);
}
}

20
hw/char/cadence_uart.c
View file

@ -143,7 +143,7 @@ static void uart_rx_reset(CadenceUARTState *s)
s->rx_wpos = 0;
s->rx_count = 0;
if (s->chr.chr) {
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
}
}
@ -157,8 +157,8 @@ static void uart_send_breaks(CadenceUARTState *s)
int break_enabled = 1;
if (s->chr.chr) {
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enabled);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enabled);
}
}
@ -211,7 +211,7 @@ static void uart_parameters_setup(CadenceUARTState *s)
packet_size += ssp.data_bits + ssp.stop_bits;
s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
if (s->chr.chr) {
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
}
@ -278,7 +278,7 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
int ret;
/* instant drain the fifo when there's no back-end */
if (!s->chr.chr) {
if (!qemu_chr_fe_get_driver(&s->chr)) {
s->tx_count = 0;
return FALSE;
}
@ -287,7 +287,7 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
return FALSE;
}
ret = qemu_chr_fe_write(s->chr.chr, s->tx_fifo, s->tx_count);
ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count);
if (ret >= 0) {
s->tx_count -= ret;
@ -295,7 +295,7 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
}
if (s->tx_count) {
guint r = qemu_chr_fe_add_watch(s->chr.chr, G_IO_OUT | G_IO_HUP,
guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
cadence_uart_xmit, s);
if (!r) {
s->tx_count = 0;
@ -369,7 +369,7 @@ static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
s->rx_count--;
if (s->chr.chr) {
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
}
} else {
*c = 0;
@ -475,8 +475,8 @@ static void cadence_uart_realize(DeviceState *dev, Error **errp)
fifo_trigger_update, s);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, uart_can_receive, uart_receive,
uart_event, s);
qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
uart_event, s, NULL);
}
}

6
hw/char/debugcon.c
View file

@ -62,7 +62,7 @@ static void debugcon_ioport_write(void *opaque, hwaddr addr, uint64_t val,
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
@ -87,12 +87,12 @@ static const MemoryRegionOps debugcon_ops = {
static void debugcon_realize_core(DebugconState *s, Error **errp)
{
if (!s->chr.chr) {
if (!qemu_chr_fe_get_driver(&s->chr)) {
error_setg(errp, "Can't create debugcon device, empty char device");
return;
}
qemu_chr_add_handlers(s->chr.chr, NULL, NULL, NULL, s);
qemu_chr_fe_set_handlers(&s->chr, NULL, NULL, NULL, s, NULL);
}
static void debugcon_isa_realizefn(DeviceState *dev, Error **errp)

5
hw/char/digic-uart.c
View file

@ -79,7 +79,7 @@ static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value,
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
break;
@ -148,7 +148,8 @@ static void digic_uart_realize(DeviceState *dev, Error **errp)
DigicUartState *s = DIGIC_UART(dev);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, uart_can_rx, uart_rx, uart_event, s);
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
}

17
hw/char/escc.c
View file

@ -416,7 +416,7 @@ static void escc_update_parameters(ChannelState *s)
int speed, parity, data_bits, stop_bits;
QEMUSerialSetParams ssp;
if (!s->chr.chr || s->type != ser)
if (!qemu_chr_fe_get_driver(&s->chr) || s->type != ser)
return;
if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) {
@ -466,7 +466,7 @@ static void escc_update_parameters(ChannelState *s)
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits);
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
static void escc_mem_write(void *opaque, hwaddr addr,
@ -556,10 +556,10 @@ static void escc_mem_write(void *opaque, hwaddr addr,
trace_escc_mem_writeb_data(CHN_C(s), val);
s->tx = val;
if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled
if (s->chr.chr) {
if (qemu_chr_fe_get_driver(&s->chr)) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &s->tx, 1);
qemu_chr_fe_write_all(&s->chr, &s->tx, 1);
} else if (s->type == kbd && !s->disabled) {
handle_kbd_command(s, val);
}
@ -600,7 +600,7 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr,
ret = s->rx;
trace_escc_mem_readb_data(CHN_C(s), ret);
if (s->chr.chr) {
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
}
return ret;
default:
@ -1014,10 +1014,11 @@ static void escc_realize(DeviceState *dev, Error **errp)
ESCC_SIZE << s->it_shift);
for (i = 0; i < 2; i++) {
if (s->chn[i].chr.chr) {
if (qemu_chr_fe_get_driver(&s->chn[i].chr)) {
s->chn[i].clock = s->frequency / 2;
qemu_chr_add_handlers(s->chn[i].chr.chr, serial_can_receive,
serial_receive1, serial_event, &s->chn[i]);
qemu_chr_fe_set_handlers(&s->chn[i].chr, serial_can_receive,
serial_receive1, serial_event,
&s->chn[i], NULL);
}
}

8
hw/char/etraxfs_ser.c
View file

@ -128,7 +128,7 @@ ser_write(void *opaque, hwaddr addr,
case RW_DOUT:
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->regs[R_INTR] |= 3;
s->pending_tx = 1;
s->regs[addr] = value;
@ -232,9 +232,9 @@ static void etraxfs_ser_realize(DeviceState *dev, Error **errp)
ETRAXSerial *s = ETRAX_SERIAL(dev);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr,
serial_can_receive, serial_receive,
serial_event, s);
qemu_chr_fe_set_handlers(&s->chr,
serial_can_receive, serial_receive,
serial_event, s, NULL);
}
}

11
hw/char/exynos4210_uart.c
View file

@ -346,7 +346,7 @@ static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
s->channel, speed, parity, data_bits, stop_bits);
@ -383,13 +383,13 @@ static void exynos4210_uart_write(void *opaque, hwaddr offset,
break;
case UTXH:
if (s->chr.chr) {
if (qemu_chr_fe_get_driver(&s->chr)) {
s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
UTRSTAT_Tx_BUFFER_EMPTY);
ch = (uint8_t)val;
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
#if DEBUG_Tx_DATA
fprintf(stderr, "%c", ch);
#endif
@ -640,8 +640,9 @@ static int exynos4210_uart_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
qemu_chr_add_handlers(s->chr.chr, exynos4210_uart_can_receive,
exynos4210_uart_receive, exynos4210_uart_event, s);
qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive,
exynos4210_uart_receive, exynos4210_uart_event,
s, NULL);
return 0;
}

15
hw/char/grlib_apbuart.c
View file

@ -201,11 +201,12 @@ static void grlib_apbuart_write(void *opaque, hwaddr addr,
case DATA_OFFSET:
case DATA_OFFSET + 3: /* When only one byte write */
/* Transmit when character device available and transmitter enabled */
if (uart->chr.chr && (uart->control & UART_TRANSMIT_ENABLE)) {
if (qemu_chr_fe_get_driver(&uart->chr) &&
(uart->control & UART_TRANSMIT_ENABLE)) {
c = value & 0xFF;
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(uart->chr.chr, &c, 1);
qemu_chr_fe_write_all(&uart->chr, &c, 1);
/* Generate interrupt */
if (uart->control & UART_TRANSMIT_INTERRUPT) {
qemu_irq_pulse(uart->irq);
@ -242,11 +243,11 @@ static int grlib_apbuart_init(SysBusDevice *dev)
{
UART *uart = GRLIB_APB_UART(dev);
qemu_chr_add_handlers(uart->chr.chr,
grlib_apbuart_can_receive,
grlib_apbuart_receive,
grlib_apbuart_event,
uart);
qemu_chr_fe_set_handlers(&uart->chr,
grlib_apbuart_can_receive,
grlib_apbuart_receive,
grlib_apbuart_event,
uart, NULL);
sysbus_init_irq(dev, &uart->irq);

14
hw/char/imx_serial.c
View file

@ -122,7 +122,7 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
s->uts1 |= UTS1_RXEMPTY;
imx_update(s);
if (s->chr.chr) {
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
}
}
return c;
@ -172,11 +172,11 @@ static void imx_serial_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
IMXSerialState *s = (IMXSerialState *)opaque;
CharDriverState *chr = qemu_chr_fe_get_driver(&s->chr);
unsigned char ch;
DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
offset, (unsigned int)value,
s->chr.chr ? s->chr.chr->label : "NODEV");
offset, (unsigned int)value, chr ? chr->label : "NODEV");
switch (offset >> 2) {
case 0x10: /* UTXD */
@ -185,7 +185,7 @@ static void imx_serial_write(void *opaque, hwaddr offset,
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
s->usr1 &= ~USR1_TRDY;
imx_update(s);
@ -216,7 +216,7 @@ static void imx_serial_write(void *opaque, hwaddr offset,
if (value & UCR2_RXEN) {
if (!(s->ucr2 & UCR2_RXEN)) {
if (s->chr.chr) {
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
}
}
}
@ -320,8 +320,8 @@ static void imx_serial_realize(DeviceState *dev, Error **errp)
IMXSerialState *s = IMX_SERIAL(dev);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, imx_can_receive, imx_receive,
imx_event, s);
qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
imx_event, s, NULL);
} else {
DPRINTF("No char dev for uart\n");
}

10
hw/char/ipoctal232.c
View file

@ -289,7 +289,7 @@ static uint16_t io_read(IPackDevice *ip, uint8_t addr)
ch->sr &= ~SR_RXRDY;
blk->isr &= ~ISR_RXRDY(channel);
if (ch->dev.chr) {
qemu_chr_fe_accept_input(ch->dev.chr);
qemu_chr_fe_accept_input(&ch->dev);
}
} else {
ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
@ -362,7 +362,7 @@ static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
uint8_t thr = reg;
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(ch->dev.chr, &thr, 1);
qemu_chr_fe_write_all(&ch->dev, &thr, 1);
}
} else {
DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
@ -546,9 +546,9 @@ static void ipoctal_realize(DeviceState *dev, Error **errp)
ch->ipoctal = s;
/* Redirect IP-Octal channels to host character devices */
if (ch->dev.chr) {
qemu_chr_add_handlers(ch->dev.chr, hostdev_can_receive,
hostdev_receive, hostdev_event, ch);
if (qemu_chr_fe_get_driver(&ch->dev)) {
qemu_chr_fe_set_handlers(&ch->dev, hostdev_can_receive,
hostdev_receive, hostdev_event, ch, NULL);
DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label);
} else {
DPRINTF("Could not redirect channel %u, no chardev set\n", i);

6
hw/char/lm32_juart.c
View file

@ -78,7 +78,7 @@ void lm32_juart_set_jtx(DeviceState *d, uint32_t jtx)
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
}
@ -121,8 +121,8 @@ static void lm32_juart_realize(DeviceState *dev, Error **errp)
LM32JuartState *s = LM32_JUART(dev);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, juart_can_rx,
juart_rx, juart_event, s);
qemu_chr_fe_set_handlers(&s->chr, juart_can_rx, juart_rx,
juart_event, s, NULL);
}
}

7
hw/char/lm32_uart.c
View file

@ -142,7 +142,7 @@ static uint64_t uart_read(void *opaque, hwaddr addr,
r = s->regs[R_RXTX];
s->regs[R_LSR] &= ~LSR_DR;
uart_update_irq(s);
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
break;
case R_IIR:
case R_LSR:
@ -180,7 +180,7 @@ static void uart_write(void *opaque, hwaddr addr,
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
break;
case R_IER:
@ -268,7 +268,8 @@ static void lm32_uart_realize(DeviceState *dev, Error **errp)
LM32UartState *s = LM32_UART(dev);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, uart_can_rx, uart_rx, uart_event, s);
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
}

8
hw/char/mcf_uart.c
View file

@ -93,7 +93,7 @@ uint64_t mcf_uart_read(void *opaque, hwaddr addr,
if (s->fifo_len == 0)
s->sr &= ~MCF_UART_RxRDY;
mcf_uart_update(s);
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
return val;
}
case 0x10:
@ -117,7 +117,7 @@ static void mcf_uart_do_tx(mcf_uart_state *s)
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, (unsigned char *)&s->tb, 1);
qemu_chr_fe_write_all(&s->chr, (unsigned char *)&s->tb, 1);
}
s->sr |= MCF_UART_TxEMP;
}
@ -286,8 +286,8 @@ void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
if (chr) {
qemu_chr_fe_init(&s->chr, chr, &error_abort);
qemu_chr_fe_claim_no_fail(chr);
qemu_chr_add_handlers(chr, mcf_uart_can_receive, mcf_uart_receive,
mcf_uart_event, s);
qemu_chr_fe_set_handlers(&s->chr, mcf_uart_can_receive,
mcf_uart_receive, mcf_uart_event, s, NULL);
}
mcf_uart_reset(s);
return s;

7
hw/char/milkymist-uart.c
View file

@ -125,7 +125,7 @@ static void uart_write(void *opaque, hwaddr addr, uint64_t value,
switch (addr) {
case R_RXTX:
if (s->chr.chr) {
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
s->regs[R_STAT] |= STAT_TX_EVT;
break;
@ -138,7 +138,7 @@ static void uart_write(void *opaque, hwaddr addr, uint64_t value,
case R_STAT:
/* write one to clear bits */
s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
break;
default:
@ -201,7 +201,8 @@ static void milkymist_uart_realize(DeviceState *dev, Error **errp)
MilkymistUartState *s = MILKYMIST_UART(dev);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, uart_can_rx, uart_rx, uart_event, s);
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
}

34
hw/char/parallel.c
View file

@ -131,7 +131,7 @@ parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
if ((s->control & PARA_CTR_STROBE) == 0)
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &s->dataw, 1);
qemu_chr_fe_write_all(&s->chr, &s->dataw, 1);
} else {
if (s->control & PARA_CTR_INTEN) {
s->irq_pending = 1;
@ -161,7 +161,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
if (s->dataw == val)
return;
pdebug("wd%02x\n", val);
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
s->dataw = val;
break;
case PARA_REG_STS:
@ -181,11 +181,11 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
} else {
dir = 0;
}
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_DATA_DIR, &dir);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
parm &= ~PARA_CTR_DIR;
}
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
s->control = val;
break;
case PARA_REG_EPP_ADDR:
@ -194,7 +194,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
pdebug("wa%02x s\n", val);
else {
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
if (qemu_chr_fe_ioctl(s->chr.chr,
if (qemu_chr_fe_ioctl(&s->chr,
CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
s->epp_timeout = 1;
pdebug("wa%02x t\n", val);
@ -209,7 +209,7 @@ static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
pdebug("we%02x s\n", val);
else {
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
if (qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
s->epp_timeout = 1;
pdebug("we%02x t\n", val);
}
@ -234,7 +234,7 @@ parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
pdebug("we%04x s\n", val);
return;
}
err = qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
if (err) {
s->epp_timeout = 1;
pdebug("we%04x t\n", val);
@ -257,7 +257,7 @@ parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
pdebug("we%08x s\n", val);
return;
}
err = qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
if (err) {
s->epp_timeout = 1;
pdebug("we%08x t\n", val);
@ -309,13 +309,13 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
addr &= 7;
switch(addr) {
case PARA_REG_DATA:
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_READ_DATA, &ret);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
if (s->last_read_offset != addr || s->datar != ret)
pdebug("rd%02x\n", ret);
s->datar = ret;
break;
case PARA_REG_STS:
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_READ_STATUS, &ret);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
ret &= ~PARA_STS_TMOUT;
if (s->epp_timeout)
ret |= PARA_STS_TMOUT;
@ -327,7 +327,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
/* s->control has some bits fixed to 1. It is zero only when
it has not been yet written to. */
if (s->control == 0) {
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
if (s->last_read_offset != addr)
pdebug("rc%02x\n", ret);
s->control = ret;
@ -345,7 +345,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
pdebug("ra%02x s\n", ret);
else {
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
if (qemu_chr_fe_ioctl(s->chr.chr,
if (qemu_chr_fe_ioctl(&s->chr,
CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
s->epp_timeout = 1;
pdebug("ra%02x t\n", ret);
@ -361,7 +361,7 @@ static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
pdebug("re%02x s\n", ret);
else {
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
if (qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
s->epp_timeout = 1;
pdebug("re%02x t\n", ret);
}
@ -389,7 +389,7 @@ parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
pdebug("re%04x s\n", eppdata);
return eppdata;
}
err = qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ret = le16_to_cpu(eppdata);
if (err) {
@ -416,7 +416,7 @@ parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
pdebug("re%08x s\n", eppdata);
return eppdata;
}
err = qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ret = le32_to_cpu(eppdata);
if (err) {
@ -512,7 +512,7 @@ static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
int base;
uint8_t dummy;
if (!s->chr.chr) {
if (!qemu_chr_fe_get_driver(&s->chr)) {
error_setg(errp, "Can't create parallel device, empty char device");
return;
}
@ -534,7 +534,7 @@ static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
isa_init_irq(isadev, &s->irq, isa->isairq);
qemu_register_reset(parallel_reset, s);
if (qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
s->hw_driver = 1;
s->status = dummy;
}

8
hw/char/pl011.c
View file

@ -88,7 +88,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
s->rsr = c >> 8;
pl011_update(s);
if (s->chr.chr) {
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
}
r = c;
break;
@ -171,7 +171,7 @@ static void pl011_write(void *opaque, hwaddr offset,
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
s->int_level |= PL011_INT_TX;
pl011_update(s);
@ -333,8 +333,8 @@ static void pl011_realize(DeviceState *dev, Error **errp)
PL011State *s = PL011(dev);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, pl011_can_receive, pl011_receive,
pl011_event, s);
qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive,
pl011_event, s, NULL);
}
}

10
hw/char/sclpconsole-lm.c
View file

@ -91,7 +91,7 @@ static void chr_read(void *opaque, const uint8_t *buf, int size)
if (scon->echo) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(scon->chr.chr, buf, size);
qemu_chr_fe_write_all(&scon->chr, buf, size);
}
}
@ -195,14 +195,14 @@ static int write_console_data(SCLPEvent *event, const uint8_t *buf, int len)
{
SCLPConsoleLM *scon = SCLPLM_CONSOLE(event);
if (!scon->chr.chr) {
if (!qemu_chr_fe_get_driver(&scon->chr)) {
/* If there's no backend, we can just say we consumed all data. */
return len;
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
return qemu_chr_fe_write_all(scon->chr.chr, buf, len);
return qemu_chr_fe_write_all(&scon->chr, buf, len);
}
static int process_mdb(SCLPEvent *event, MDBO *mdbo)
@ -313,8 +313,8 @@ static int console_init(SCLPEvent *event)
console_available = true;
if (scon->chr.chr) {
qemu_chr_add_handlers(scon->chr.chr, chr_can_read,
chr_read, NULL, scon);
qemu_chr_fe_set_handlers(&scon->chr, chr_can_read,
chr_read, NULL, scon, NULL);
}
return 0;

8
hw/char/sclpconsole.c
View file

@ -163,14 +163,14 @@ static ssize_t write_console_data(SCLPEvent *event, const uint8_t *buf,
{
SCLPConsole *scon = SCLP_CONSOLE(event);
if (!scon->chr.chr) {
if (!qemu_chr_fe_get_driver(&scon->chr)) {
/* If there's no backend, we can just say we consumed all data. */
return len;
}
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
return qemu_chr_fe_write_all(scon->chr.chr, buf, len);
return qemu_chr_fe_write_all(&scon->chr, buf, len);
}
static int write_event_data(SCLPEvent *event, EventBufferHeader *evt_buf_hdr)
@ -228,8 +228,8 @@ static int console_init(SCLPEvent *event)
}
console_available = true;
if (scon->chr.chr) {
qemu_chr_add_handlers(scon->chr.chr, chr_can_read,
chr_read, NULL, scon);
qemu_chr_fe_set_handlers(&scon->chr, chr_can_read,
chr_read, NULL, scon, NULL);
}
return 0;

30
hw/char/serial.c
View file

@ -182,7 +182,7 @@ static void serial_update_parameters(SerialState *s)
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size;
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
speed, parity, data_bits, stop_bits);
@ -195,7 +195,7 @@ static void serial_update_msl(SerialState *s)
timer_del(s->modem_status_poll);
if (qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_GET_TIOCM,
if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM,
&flags) == -ENOTSUP) {
s->poll_msl = -1;
return;
@ -261,11 +261,11 @@ static void serial_xmit(SerialState *s)
if (s->mcr & UART_MCR_LOOP) {
/* in loopback mode, say that we just received a char */
serial_receive1(s, &s->tsr, 1);
} else if (qemu_chr_fe_write(s->chr.chr, &s->tsr, 1) != 1 &&
} else if (qemu_chr_fe_write(&s->chr, &s->tsr, 1) != 1 &&
s->tsr_retry < MAX_XMIT_RETRY) {
assert(s->watch_tag == 0);
s->watch_tag =
qemu_chr_fe_add_watch(s->chr.chr, G_IO_OUT | G_IO_HUP,
qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
serial_watch_cb, s);
if (s->watch_tag > 0) {
s->tsr_retry++;
@ -419,8 +419,8 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
break_enable = (val >> 6) & 1;
if (break_enable != s->last_break_enable) {
s->last_break_enable = break_enable;
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enable);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enable);
}
}
break;
@ -434,8 +434,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
if (s->poll_msl >= 0 && old_mcr != s->mcr) {
qemu_chr_fe_ioctl(s->chr.chr,
CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
@ -444,8 +443,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
if (val & UART_MCR_DTR)
flags |= CHR_TIOCM_DTR;
qemu_chr_fe_ioctl(s->chr.chr,
CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
/* Update the modem status after a one-character-send wait-time, since there may be a response
from the device/computer at the other end of the serial line */
timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time);
@ -490,7 +488,7 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
serial_update_irq(s);
if (!(s->mcr & UART_MCR_LOOP)) {
/* in loopback mode, don't receive any data */
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
}
}
break;
@ -663,7 +661,7 @@ static int serial_post_load(void *opaque, int version_id)
}
assert(s->watch_tag == 0);
s->watch_tag = qemu_chr_fe_add_watch(s->chr.chr, G_IO_OUT | G_IO_HUP,
s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
serial_watch_cb, s);
} else {
/* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty). */
@ -888,7 +886,7 @@ static void serial_reset(void *opaque)
void serial_realize_core(SerialState *s, Error **errp)
{
if (!s->chr.chr) {
if (!qemu_chr_fe_get_driver(&s->chr)) {
error_setg(errp, "Can't create serial device, empty char device");
return;
}
@ -898,8 +896,8 @@ void serial_realize_core(SerialState *s, Error **errp)
s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
qemu_register_reset(serial_reset, s);
qemu_chr_add_handlers(s->chr.chr, serial_can_receive1, serial_receive1,
serial_event, s);
qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
serial_event, s, NULL);
fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
serial_reset(s);
@ -907,7 +905,7 @@ void serial_realize_core(SerialState *s, Error **errp)
void serial_exit_core(SerialState *s)
{
qemu_chr_add_handlers(s->chr.chr, NULL, NULL, NULL, NULL);
qemu_chr_fe_set_handlers(&s->chr, NULL, NULL, NULL, NULL, NULL);
qemu_unregister_reset(serial_reset, s);
}

9
hw/char/sh_serial.c
View file

@ -110,11 +110,11 @@ static void sh_serial_write(void *opaque, hwaddr offs,
}
return;
case 0x0c: /* FTDR / TDR */
if (s->chr.chr) {
if (qemu_chr_fe_get_driver(&s->chr)) {
ch = val;
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
s->dr = val;
s->flags &= ~SH_SERIAL_FLAG_TDE;
@ -399,8 +399,9 @@ void sh_serial_init(MemoryRegion *sysmem,
if (chr) {
qemu_chr_fe_claim_no_fail(chr);
qemu_chr_fe_init(&s->chr, chr, &error_abort);
qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
sh_serial_event, s);
qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
sh_serial_receive1,
sh_serial_event, s, NULL);
}
s->eri = eri_source;

10
hw/char/spapr_vty.c
View file

@ -51,7 +51,7 @@ static int vty_getchars(VIOsPAPRDevice *sdev, uint8_t *buf, int max)
buf[n++] = dev->buf[dev->out++ % VTERM_BUFSIZE];
}
qemu_chr_fe_accept_input(dev->chardev.chr);
qemu_chr_fe_accept_input(&dev->chardev);
return n;
}
@ -62,20 +62,20 @@ void vty_putchars(VIOsPAPRDevice *sdev, uint8_t *buf, int len)
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(dev->chardev.chr, buf, len);
qemu_chr_fe_write_all(&dev->chardev, buf, len);
}
static void spapr_vty_realize(VIOsPAPRDevice *sdev, Error **errp)
{
VIOsPAPRVTYDevice *dev = VIO_SPAPR_VTY_DEVICE(sdev);
if (!dev->chardev.chr) {
if (!qemu_chr_fe_get_driver(&dev->chardev)) {
error_setg(errp, "chardev property not set");
return;
}
qemu_chr_add_handlers(dev->chardev.chr, vty_can_receive,
vty_receive, NULL, dev);
qemu_chr_fe_set_handlers(&dev->chardev, vty_can_receive,
vty_receive, NULL, dev, NULL);
}
/* Forward declaration */

10
hw/char/stm32f2xx_usart.c
View file

@ -98,7 +98,7 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
retvalue = s->usart_sr;
s->usart_sr &= ~USART_SR_TC;
if (s->chr.chr) {
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
}
return retvalue;
case USART_DR:
@ -106,7 +106,7 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
s->usart_sr |= USART_SR_TXE;
s->usart_sr &= ~USART_SR_RXNE;
if (s->chr.chr) {
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
}
qemu_set_irq(s->irq, 0);
return s->usart_dr & 0x3FF;
@ -155,7 +155,7 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
s->usart_sr |= USART_SR_TC;
s->usart_sr &= ~USART_SR_TXE;
@ -213,8 +213,8 @@ static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp)
STM32F2XXUsartState *s = STM32F2XX_USART(dev);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, stm32f2xx_usart_can_receive,
stm32f2xx_usart_receive, NULL, s);
qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive,
stm32f2xx_usart_receive, NULL, s, NULL);
}
}

27
hw/char/virtio-console.c
View file

@ -49,12 +49,12 @@ static ssize_t flush_buf(VirtIOSerialPort *port,
VirtConsole *vcon = VIRTIO_CONSOLE(port);
ssize_t ret;
if (!vcon->chr.chr) {
if (!qemu_chr_fe_get_driver(&vcon->chr)) {
/* If there's no backend, we can just say we consumed all data. */
return len;
}
ret = qemu_chr_fe_write(vcon->chr.chr, buf, len);
ret = qemu_chr_fe_write(&vcon->chr, buf, len);
trace_virtio_console_flush_buf(port->id, len, ret);
if (ret < len) {
@ -92,8 +92,8 @@ static ssize_t flush_buf(VirtIOSerialPort *port,
if (!k->is_console) {
virtio_serial_throttle_port(port, true);
if (!vcon->watch) {
vcon->watch = qemu_chr_fe_add_watch(vcon->chr.chr,
G_IO_OUT | G_IO_HUP,
vcon->watch = qemu_chr_fe_add_watch(&vcon->chr,
G_IO_OUT|G_IO_HUP,
chr_write_unblocked, vcon);
}
}
@ -109,7 +109,7 @@ static void set_guest_connected(VirtIOSerialPort *port, int guest_connected)
VirtIOSerialPortClass *k = VIRTIO_SERIAL_PORT_GET_CLASS(port);
if (vcon->chr.chr && !k->is_console) {
qemu_chr_fe_set_open(vcon->chr.chr, guest_connected);
qemu_chr_fe_set_open(&vcon->chr, guest_connected);
}
if (dev->id) {
@ -123,7 +123,7 @@ static void guest_writable(VirtIOSerialPort *port)
VirtConsole *vcon = VIRTIO_CONSOLE(port);
if (vcon->chr.chr) {
qemu_chr_fe_accept_input(vcon->chr.chr);
qemu_chr_fe_accept_input(&vcon->chr);
}
}
@ -170,6 +170,7 @@ static void virtconsole_realize(DeviceState *dev, Error **errp)
VirtIOSerialPort *port = VIRTIO_SERIAL_PORT(dev);
VirtConsole *vcon = VIRTIO_CONSOLE(dev);
VirtIOSerialPortClass *k = VIRTIO_SERIAL_PORT_GET_CLASS(dev);
CharDriverState *chr = qemu_chr_fe_get_driver(&vcon->chr);
if (port->id == 0 && !k->is_console) {
error_setg(errp, "Port number 0 on virtio-serial devices reserved "
@ -177,7 +178,7 @@ static void virtconsole_realize(DeviceState *dev, Error **errp)
return;
}
if (vcon->chr.chr) {
if (chr) {
/*
* For consoles we don't block guest data transfer just
* because nothing is connected - we'll just let it go
@ -188,14 +189,14 @@ static void virtconsole_realize(DeviceState *dev, Error **errp)
* trigger open/close of the device
*/
if (k->is_console) {
vcon->chr.chr->explicit_fe_open = 0;
qemu_chr_add_handlers(vcon->chr.chr, chr_can_read, chr_read,
NULL, vcon);
chr->explicit_fe_open = 0;
qemu_chr_fe_set_handlers(&vcon->chr, chr_can_read, chr_read,
NULL, vcon, NULL);
virtio_serial_open(port);
} else {
vcon->chr.chr->explicit_fe_open = 1;
qemu_chr_add_handlers(vcon->chr.chr, chr_can_read, chr_read,
chr_event, vcon);
chr->explicit_fe_open = 1;
qemu_chr_fe_set_handlers(&vcon->chr, chr_can_read, chr_read,
chr_event, vcon, NULL);
}
}
}

14
hw/char/xen_console.c
View file

@ -23,6 +23,7 @@
#include <sys/select.h>
#include <termios.h>
#include "qapi/error.h"
#include "hw/hw.h"
#include "sysemu/char.h"
#include "hw/xen/xen_backend.h"
@ -149,8 +150,8 @@ static void xencons_send(struct XenConsole *con)
ssize_t len, size;
size = con->buffer.size - con->buffer.consumed;
if (con->chr.chr) {
len = qemu_chr_fe_write(con->chr.chr,
if (qemu_chr_fe_get_driver(&con->chr)) {
len = qemu_chr_fe_write(&con->chr,
con->buffer.data + con->buffer.consumed,
size);
} else {
@ -209,7 +210,8 @@ static int con_init(struct XenDevice *xendev)
qemu_chr_new(label, output), &error_abort);
}
xenstore_store_pv_console_info(con->xendev.dev, con->chr.chr);
xenstore_store_pv_console_info(con->xendev.dev,
qemu_chr_fe_get_driver(&con->chr));
out:
g_free(type);
@ -244,8 +246,8 @@ static int con_initialise(struct XenDevice *xendev)
xen_be_bind_evtchn(&con->xendev);
if (con->chr.chr) {
if (qemu_chr_fe_claim(con->chr.chr) == 0) {
qemu_chr_add_handlers(con->chr.chr, xencons_can_receive,
xencons_receive, NULL, con);
qemu_chr_fe_set_handlers(&con->chr, xencons_can_receive,
xencons_receive, NULL, con, NULL);
} else {
xen_be_printf(xendev, 0,
"xen_console_init error chardev %s already used\n",
@ -267,7 +269,7 @@ static void con_disconnect(struct XenDevice *xendev)
struct XenConsole *con = container_of(xendev, struct XenConsole, xendev);
if (con->chr.chr) {
qemu_chr_add_handlers(con->chr.chr, NULL, NULL, NULL, NULL);
qemu_chr_fe_set_handlers(&con->chr, NULL, NULL, NULL, NULL, NULL);
qemu_chr_fe_release(con->chr.chr);
}
xen_be_unbind_evtchn(&con->xendev);

7
hw/char/xilinx_uartlite.c
View file

@ -107,7 +107,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
s->rx_fifo_len--;
uart_update_status(s);
uart_update_irq(s);
qemu_chr_fe_accept_input(s->chr.chr);
qemu_chr_fe_accept_input(&s->chr);
break;
default:
@ -146,7 +146,7 @@ uart_write(void *opaque, hwaddr addr,
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
s->regs[addr] = value;
@ -214,7 +214,8 @@ static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
XilinxUARTLite *s = XILINX_UARTLITE(dev);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, uart_can_rx, uart_rx, uart_event, s);
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, s, NULL);
}
}