mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 08:13:54 -06:00
target/riscv: Use RISCVException enum for CSR access
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
This commit is contained in:
parent
605def6eee
commit
533c91e8f2
4 changed files with 38 additions and 36 deletions
|
@ -71,7 +71,7 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
|
|||
*/
|
||||
result = riscv_csrrw_debug(env, n - 32, &val,
|
||||
0, 0);
|
||||
if (result == 0) {
|
||||
if (result == RISCV_EXCP_NONE) {
|
||||
return gdb_get_regl(buf, val);
|
||||
}
|
||||
}
|
||||
|
@ -94,7 +94,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
|
|||
*/
|
||||
result = riscv_csrrw_debug(env, n - 32, NULL,
|
||||
val, -1);
|
||||
if (result == 0) {
|
||||
if (result == RISCV_EXCP_NONE) {
|
||||
return sizeof(target_ulong);
|
||||
}
|
||||
}
|
||||
|
@ -108,7 +108,7 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
|
|||
int result;
|
||||
|
||||
result = riscv_csrrw_debug(env, n, &val, 0, 0);
|
||||
if (result == 0) {
|
||||
if (result == RISCV_EXCP_NONE) {
|
||||
return gdb_get_regl(buf, val);
|
||||
}
|
||||
}
|
||||
|
@ -122,7 +122,7 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
|
|||
int result;
|
||||
|
||||
result = riscv_csrrw_debug(env, n, NULL, val, -1);
|
||||
if (result == 0) {
|
||||
if (result == RISCV_EXCP_NONE) {
|
||||
return sizeof(target_ulong);
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue