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target/arm: Simplify tlb_force_broadcast alternatives

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Rather than call to a separate function and re-compute any
parameters for the flush, simply use the correct flush
function directly.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-07 14:04:22 +00:00 • committed by Peter Maydell
parent 90c19cdf1d
commit 527db2be8b
1 changed files with 24 additions and 28 deletions
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52
target/arm/helper.c
View file

@ -614,56 +614,54 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* Invalidate all (TLBIALL) */ /* Invalidate all (TLBIALL) */
ARMCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env);
if (tlb_force_broadcast(env)) { if (tlb_force_broadcast(env)) {
tlbiall_is_write(env, NULL, value); tlb_flush_all_cpus_synced(cs);
return; } else {
tlb_flush(cs);
} }
tlb_flush(CPU(cpu));
} }
static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
ARMCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env);
value &= TARGET_PAGE_MASK;
if (tlb_force_broadcast(env)) { if (tlb_force_broadcast(env)) {
tlbimva_is_write(env, NULL, value); tlb_flush_page_all_cpus_synced(cs, value);
return; } else {
tlb_flush_page(cs, value);
} }
tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
} }
static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* Invalidate by ASID (TLBIASID) */ /* Invalidate by ASID (TLBIASID) */
ARMCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env);
if (tlb_force_broadcast(env)) { if (tlb_force_broadcast(env)) {
tlbiasid_is_write(env, NULL, value); tlb_flush_all_cpus_synced(cs);
return; } else {
tlb_flush(cs);
} }
tlb_flush(CPU(cpu));
} }
static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
ARMCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env);
value &= TARGET_PAGE_MASK;
if (tlb_force_broadcast(env)) { if (tlb_force_broadcast(env)) {
tlbimvaa_is_write(env, NULL, value); tlb_flush_page_all_cpus_synced(cs, value);
return; } else {
tlb_flush_page(cs, value);
} }
tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
} }
static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -3965,11 +3963,10 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
int mask = vae1_tlbmask(env); int mask = vae1_tlbmask(env);
if (tlb_force_broadcast(env)) { if (tlb_force_broadcast(env)) {
tlbi_aa64_vmalle1is_write(env, NULL, value); tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
return; } else {
}
tlb_flush_by_mmuidx(cs, mask); tlb_flush_by_mmuidx(cs, mask);
}
} }
static int alle1_tlbmask(CPUARMState *env) static int alle1_tlbmask(CPUARMState *env)
@ -4091,11 +4088,10 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t pageaddr = sextract64(value << 12, 0, 56); uint64_t pageaddr = sextract64(value << 12, 0, 56);
if (tlb_force_broadcast(env)) { if (tlb_force_broadcast(env)) {
tlbi_aa64_vae1is_write(env, NULL, value); tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
return; } else {
}
tlb_flush_page_by_mmuidx(cs, pageaddr, mask); tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
} }
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,