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target/ppc: Add POWER10 exception model

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POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
and it removes support for the LPCR[AIL]=0b10 mode.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210501072436.145444-3-npiggin@gmail.com>
[dwg: Corrected tab indenting]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nicholas Piggin 2021-05-01 17:24:35 +10:00 • committed by David Gibson
parent 8b7e6b07a4
commit 526cdce771
6 changed files with 65 additions and 8 deletions
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54
target/ppc/excp_helper.c
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@ -170,7 +170,27 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
* +-------------------------------------------------------+
*
* The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to
* the hypervisor in AIL mode if the guest is radix.
* the hypervisor in AIL mode if the guest is radix. This is good for
* performance but allows the guest to influence the AIL of hypervisor
* interrupts using its MSR, and also the hypervisor must disallow guest
* interrupts (MSR[HV] 0->0) from using AIL if the hypervisor does not want to
* use AIL for its MSR[HV] 0->1 interrupts.
*
* POWER10 addresses those issues with a new LPCR[HAIL] bit that is applied to
* interrupts that begin execution with MSR[HV]=1 (so both MSR[HV] 0->1 and
* MSR[HV] 1->1).
*
* HAIL=1 is equivalent to AIL=3, for interrupts delivered with MSR[HV]=1.
*
* POWER10 behaviour is
* | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
* +-----------+------------+-------------+---------+-------------+-----+
* | a | h | 00/01/10 | 0 | 0 | 0 |
* | a | h | 11 | 0 | 0 | a |
* | a | h | x | 0 | 1 | h |
* | a | h | 00/01/10 | 1 | 1 | 0 |
* | a | h | 11 | 1 | 1 | h |
* +--------------------------------------------------------------------+
*/
static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
target_ulong msr,
@ -213,6 +233,32 @@ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
/* AIL=1 is reserved, treat it like AIL=0 */
return;
}
} else if (excp_model == POWERPC_EXCP_POWER10) {
if (!mmu_all_on && !hv_escalation) {
/*
* AIL works for HV interrupts even with guest MSR[IR/DR] disabled.
* Guest->guest and HV->HV interrupts do require MMU on.
*/
return;
}
if (*new_msr & MSR_HVB) {
if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) {
/* HV interrupts depend on LPCR[HAIL] */
return;
}
ail = 3; /* HAIL=1 gives AIL=3 behaviour for HV interrupts */
} else {
ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
}
if (ail == 0) {
return;
}
if (ail == 1 || ail == 2) {
/* AIL=1 and AIL=2 are reserved, treat them like AIL=0 */
return;
}
} else {
/* Other processors do not support AIL */
return;
@ -328,7 +374,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
#if defined(TARGET_PPC64)
if (excp_model == POWERPC_EXCP_POWER7 ||
excp_model == POWERPC_EXCP_POWER8 ||
excp_model == POWERPC_EXCP_POWER9) {
excp_model == POWERPC_EXCP_POWER9 ||
excp_model == POWERPC_EXCP_POWER10) {
lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
} else
#endif /* defined(TARGET_PPC64) */
@ -848,7 +895,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
} else if (env->spr[SPR_LPCR] & LPCR_ILE) {
new_msr |= (target_ulong)1 << MSR_LE;
}
} else if (excp_model == POWERPC_EXCP_POWER9) {
} else if (excp_model == POWERPC_EXCP_POWER9 ||
excp_model == POWERPC_EXCP_POWER10) {
if (new_msr & MSR_HVB) {
if (env->spr[SPR_HID0] & HID0_POWER9_HILE) {
new_msr |= (target_ulong)1 << MSR_LE;