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target-i386: Implement CPUID[0xB] (Extended Topology Enumeration)

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I looked at a dozen Intel CPU that have this CPUID and all of them
always had Core offset as 1 (a wasted bit when hyperthreading is
disabled) and Package offset at least 4 (wasted bits at <= 4 cores).

QEMU uses more compact IDs and it doesn't make much sense to change it
now.  I keep the SMT and Core sub-leaves even if there is just one
thread/core;  it makes the code simpler and there should be no harm.

Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Radim Krčmář 2016-05-12 19:24:26 +02:00 • committed by Eduardo Habkost
parent d86c145114
commit 5232d00a04
3 changed files with 46 additions and 1 deletions
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7
include/hw/i386/pc.h
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@ -357,7 +357,12 @@ int e820_get_num_entries(void);
bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
#define PC_COMPAT_2_6 \
HW_COMPAT_2_6
HW_COMPAT_2_6 \
{\
.driver = TYPE_X86_CPU,\
.property = "cpuid-0xb",\
.value = "off",\
},
#define PC_COMPAT_2_5 \
PC_COMPAT_2_6 \