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https://github.com/Motorhead1991/qemu.git
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rust: hpet: decode HPET registers into enums
Generalize timer_and_addr() to decode all registers into a single enum HPETRegister, and use the TryInto derive to separate valid and invalid values. The main advantage lies in checking that all registers are enumerated in the "match" statements. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
aa50bc4fb9
commit
519088b7cf
3 changed files with 119 additions and 107 deletions
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@ -37,6 +37,8 @@ result_unit_err = "allow"
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should_implement_trait = "deny"
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# can be for a reason, e.g. in callbacks
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unused_self = "allow"
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# common in device crates
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upper_case_acronyms = "allow"
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# default-allow lints
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as_ptr_cast_mut = "deny"
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@ -12,8 +12,6 @@
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//! See [`PL011State`](crate::device::PL011State) for the device model type and
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//! the [`registers`] module for register types.
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#![allow(clippy::upper_case_acronyms)]
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use qemu_api::c_str;
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mod device;
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@ -48,8 +48,6 @@ const RTC_ISA_IRQ: usize = 8;
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const HPET_CLK_PERIOD: u64 = 10; // 10 ns
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const FS_PER_NS: u64 = 1000000; // 1000000 femtoseconds == 1 ns
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/// General Capabilities and ID Register
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const HPET_CAP_REG: u64 = 0x000;
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/// Revision ID (bits 0:7). Revision 1 is implemented (refer to v1.0a spec).
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const HPET_CAP_REV_ID_VALUE: u64 = 0x1;
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const HPET_CAP_REV_ID_SHIFT: usize = 0;
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@ -65,8 +63,6 @@ const HPET_CAP_VENDER_ID_SHIFT: usize = 16;
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/// Main Counter Tick Period (bits 32:63)
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const HPET_CAP_CNT_CLK_PERIOD_SHIFT: usize = 32;
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/// General Configuration Register
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const HPET_CFG_REG: u64 = 0x010;
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/// Overall Enable (bit 0)
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const HPET_CFG_ENABLE_SHIFT: usize = 0;
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/// Legacy Replacement Route (bit 1)
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@ -74,14 +70,6 @@ const HPET_CFG_LEG_RT_SHIFT: usize = 1;
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/// Other bits are reserved.
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const HPET_CFG_WRITE_MASK: u64 = 0x003;
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/// General Interrupt Status Register
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const HPET_INT_STATUS_REG: u64 = 0x020;
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/// Main Counter Value Register
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const HPET_COUNTER_REG: u64 = 0x0f0;
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/// Timer N Configuration and Capability Register (masked by 0x18)
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const HPET_TN_CFG_REG: u64 = 0x000;
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/// bit 0, 7, and bits 16:31 are reserved.
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/// bit 4, 5, 15, and bits 32:64 are read-only.
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const HPET_TN_CFG_WRITE_MASK: u64 = 0x7f4e;
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@ -109,11 +97,51 @@ const HPET_TN_CFG_FSB_CAP_SHIFT: usize = 15;
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/// Timer N Interrupt Routing Capability (bits 32:63)
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const HPET_TN_CFG_INT_ROUTE_CAP_SHIFT: usize = 32;
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/// Timer N Comparator Value Register (masked by 0x18)
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const HPET_TN_CMP_REG: u64 = 0x008;
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#[derive(qemu_api_macros::TryInto)]
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#[repr(u64)]
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#[allow(non_camel_case_types)]
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/// Timer registers, masked by 0x18
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enum TimerRegister {
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/// Timer N Configuration and Capability Register
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CFG = 0,
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/// Timer N Comparator Value Register
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CMP = 8,
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/// Timer N FSB Interrupt Route Register
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ROUTE = 16,
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}
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/// Timer N FSB Interrupt Route Register (masked by 0x18)
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const HPET_TN_FSB_ROUTE_REG: u64 = 0x010;
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#[derive(qemu_api_macros::TryInto)]
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#[repr(u64)]
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#[allow(non_camel_case_types)]
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/// Global registers
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enum GlobalRegister {
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/// General Capabilities and ID Register
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CAP = 0,
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/// General Configuration Register
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CFG = 0x10,
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/// General Interrupt Status Register
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INT_STATUS = 0x20,
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/// Main Counter Value Register
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COUNTER = 0xF0,
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}
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enum HPETRegister<'a> {
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/// Global register in the range from `0` to `0xff`
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Global(GlobalRegister),
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/// Register in the timer block `0x100`...`0x3ff`
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Timer(&'a BqlRefCell<HPETTimer>, TimerRegister),
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/// Invalid address
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#[allow(dead_code)]
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Unknown(hwaddr),
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}
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struct HPETAddrDecode<'a> {
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shift: u32,
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len: u32,
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reg: HPETRegister<'a>,
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}
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const fn hpet_next_wrap(cur_tick: u64) -> u64 {
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(cur_tick | 0xffffffff) + 1
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@ -471,33 +499,21 @@ impl HPETTimer {
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self.update_irq(true);
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}
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const fn read(&self, addr: hwaddr, _size: u32) -> u64 {
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let shift: u64 = (addr & 4) * 8;
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match addr & !4 {
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HPET_TN_CFG_REG => self.config >> shift, // including interrupt capabilities
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HPET_TN_CMP_REG => self.cmp >> shift, // comparator register
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HPET_TN_FSB_ROUTE_REG => self.fsb >> shift,
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_ => {
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// TODO: Add trace point - trace_hpet_ram_read_invalid()
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// Reserved.
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0
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}
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const fn read(&self, reg: TimerRegister) -> u64 {
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use TimerRegister::*;
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match reg {
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CFG => self.config, // including interrupt capabilities
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CMP => self.cmp, // comparator register
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ROUTE => self.fsb,
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}
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}
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fn write(&mut self, addr: hwaddr, value: u64, size: u32) {
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let shift = ((addr & 4) * 8) as u32;
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let len = std::cmp::min(size * 8, 64 - shift);
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match addr & !4 {
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HPET_TN_CFG_REG => self.set_tn_cfg_reg(shift, len, value),
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HPET_TN_CMP_REG => self.set_tn_cmp_reg(shift, len, value),
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HPET_TN_FSB_ROUTE_REG => self.set_tn_fsb_route_reg(shift, len, value),
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_ => {
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// TODO: Add trace point - trace_hpet_ram_write_invalid()
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// Reserved.
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}
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fn write(&mut self, reg: TimerRegister, value: u64, shift: u32, len: u32) {
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use TimerRegister::*;
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match reg {
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CFG => self.set_tn_cfg_reg(shift, len, value),
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CMP => self.set_tn_cmp_reg(shift, len, value),
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ROUTE => self.set_tn_fsb_route_reg(shift, len, value),
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}
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}
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}
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@ -749,77 +765,73 @@ impl HPETState {
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self.rtc_irq_level.set(0);
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}
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fn timer_and_addr(&self, addr: hwaddr) -> Option<(&BqlRefCell<HPETTimer>, hwaddr)> {
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let timer_id: usize = ((addr - 0x100) / 0x20) as usize;
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// TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(timer_id)
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if timer_id > self.num_timers.get() {
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// TODO: Add trace point - trace_hpet_timer_id_out_of_range(timer_id)
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None
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} else {
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// Keep the complete address so that HPETTimer's read and write could
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// detect the invalid access.
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Some((&self.timers[timer_id], addr & 0x1F))
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}
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}
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fn read(&self, addr: hwaddr, size: u32) -> u64 {
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let shift: u64 = (addr & 4) * 8;
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// address range of all TN regs
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// TODO: Add trace point - trace_hpet_ram_read(addr)
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if (0x100..=0x3ff).contains(&addr) {
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match self.timer_and_addr(addr) {
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None => 0, // Reserved,
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Some((timer, tn_addr)) => timer.borrow_mut().read(tn_addr, size),
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}
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} else {
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match addr & !4 {
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HPET_CAP_REG => self.capability.get() >> shift, /* including HPET_PERIOD 0x004 */
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// (CNT_CLK_PERIOD field)
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HPET_CFG_REG => self.config.get() >> shift,
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HPET_COUNTER_REG => {
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let cur_tick: u64 = if self.is_hpet_enabled() {
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self.get_ticks()
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} else {
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self.counter.get()
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};
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// TODO: Add trace point - trace_hpet_ram_read_reading_counter(addr & 4,
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// cur_tick)
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cur_tick >> shift
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}
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HPET_INT_STATUS_REG => self.int_status.get() >> shift,
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_ => {
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// TODO: Add trace point- trace_hpet_ram_read_invalid()
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// Reserved.
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0
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}
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}
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}
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}
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fn write(&self, addr: hwaddr, value: u64, size: u32) {
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fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAddrDecode {
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let shift = ((addr & 4) * 8) as u32;
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let len = std::cmp::min(size * 8, 64 - shift);
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// TODO: Add trace point - trace_hpet_ram_write(addr, value)
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if (0x100..=0x3ff).contains(&addr) {
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match self.timer_and_addr(addr) {
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None => (), // Reserved.
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Some((timer, tn_addr)) => timer.borrow_mut().write(tn_addr, value, size),
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}
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addr &= !4;
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let reg = if (0..=0xff).contains(&addr) {
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GlobalRegister::try_from(addr).map(HPETRegister::Global)
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} else {
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match addr & !0x4 {
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HPET_CAP_REG => {} // General Capabilities and ID Register: Read Only
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HPET_CFG_REG => self.set_cfg_reg(shift, len, value),
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HPET_INT_STATUS_REG => self.set_int_status_reg(shift, len, value),
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HPET_COUNTER_REG => self.set_counter_reg(shift, len, value),
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_ => {
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// TODO: Add trace point - trace_hpet_ram_write_invalid()
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// Reserved.
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let timer_id: usize = ((addr - 0x100) / 0x20) as usize;
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if timer_id <= self.num_timers.get() {
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// TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(timer_id)
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TimerRegister::try_from(addr)
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.map(|reg| HPETRegister::Timer(&self.timers[timer_id], reg))
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} else {
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// TODO: Add trace point - trace_hpet_timer_id_out_of_range(timer_id)
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Err(addr)
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}
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};
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// reg is now a Result<HPETRegister, hwaddr>
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// convert the Err case into HPETRegister as well
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let reg = reg.unwrap_or_else(HPETRegister::Unknown);
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HPETAddrDecode { shift, len, reg }
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}
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fn read(&self, addr: hwaddr, size: u32) -> u64 {
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// TODO: Add trace point - trace_hpet_ram_read(addr)
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let HPETAddrDecode { shift, reg, .. } = self.decode(addr, size);
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use GlobalRegister::*;
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use HPETRegister::*;
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(match reg {
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Timer(timer, tn_reg) => timer.borrow_mut().read(tn_reg),
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Global(CAP) => self.capability.get(), /* including HPET_PERIOD 0x004 */
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Global(CFG) => self.config.get(),
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Global(INT_STATUS) => self.int_status.get(),
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Global(COUNTER) => {
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// TODO: Add trace point
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// trace_hpet_ram_read_reading_counter(addr & 4, cur_tick)
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if self.is_hpet_enabled() {
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self.get_ticks()
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} else {
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self.counter.get()
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}
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}
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Unknown(_) => {
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// TODO: Add trace point- trace_hpet_ram_read_invalid()
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0
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}
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}) >> shift
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}
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fn write(&self, addr: hwaddr, value: u64, size: u32) {
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let HPETAddrDecode { shift, len, reg } = self.decode(addr, size);
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// TODO: Add trace point - trace_hpet_ram_write(addr, value)
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use GlobalRegister::*;
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use HPETRegister::*;
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match reg {
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Timer(timer, tn_reg) => timer.borrow_mut().write(tn_reg, value, shift, len),
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Global(CAP) => {} // General Capabilities and ID Register: Read Only
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Global(CFG) => self.set_cfg_reg(shift, len, value),
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Global(INT_STATUS) => self.set_int_status_reg(shift, len, value),
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Global(COUNTER) => self.set_counter_reg(shift, len, value),
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Unknown(_) => {
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// TODO: Add trace point - trace_hpet_ram_write_invalid()
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}
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}
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}
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}
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