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QOM CPUState refactorings

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* Fix for OpenRISCCPU subclasses
 * Fix for gdbstub CPU selection
 * Move linux-user CPU functions into new header
 * CPUState part 10 refactoring: first_cpu, next_cpu, cpu_single_env et al.
 * Fix some targets to consistently inline TCG code generation
 * Centrally log CPU reset
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Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging

QOM CPUState refactorings

* Fix for OpenRISCCPU subclasses
* Fix for gdbstub CPU selection
* Move linux-user CPU functions into new header
* CPUState part 10 refactoring: first_cpu, next_cpu, cpu_single_env et al.
* Fix some targets to consistently inline TCG code generation
* Centrally log CPU reset

# gpg: Signature made Wed 10 Jul 2013 07:52:39 AM CDT using RSA key ID 3E7E013F
# gpg: Can't check signature: public key not found

# By Andreas Färber (41) and others
# Via Andreas Färber
* afaerber/tags/qom-cpu-for-anthony: (43 commits)
  cpu: Move reset logging to CPUState
  target-ppc: Change LOG_MMU_STATE() argument to CPUState
  target-i386: Change LOG_PCALL_STATE() argument to CPUState
  log: Change log_cpu_state[_mask]() argument to CPUState
  target-i386: Change do_smm_enter() argument to X86CPU
  target-i386: Change do_interrupt_all() argument to X86CPU
  target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU
  target-unicore32: Change gen_intermediate_code_internal() signature
  target-sparc: Change gen_intermediate_code_internal() argument to SPARCCPU
  target-sh4: Change gen_intermediate_code_internal() argument to SuperHCPU
  target-s390x: Change gen_intermediate_code_internal() argument to S390CPU
  target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPU
  target-mips: Change gen_intermediate_code_internal() argument to MIPSCPU
  target-microblaze: Change gen_intermediate_code_internal() argument types
  target-m68k: Change gen_intermediate_code_internal() argument to M68kCPU
  target-lm32: Change gen_intermediate_code_internal() argument to LM32CPU
  target-i386: Change gen_intermediate_code_internal() argument to X86CPU
  target-cris: Change gen_intermediate_code_internal() argument to CRISCPU
  target-arm: Change gen_intermediate_code_internal() argument to ARMCPU
  target-alpha: Change gen_intermediate_code_internal() argument to AlphaCPU
  ...
This commit is contained in:
Anthony Liguori 2013-07-10 10:54:16 -05:00
commit 51455c59dd
153 changed files with 1140 additions and 831 deletions
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57
exec.c
View file

@ -69,10 +69,10 @@ static MemoryRegion io_mem_unassigned;
#endif
CPUArchState *first_cpu;
CPUState *first_cpu;
/* current CPU in the current thread. It is only valid inside
cpu_exec() */
DEFINE_TLS(CPUArchState *,cpu_single_env);
DEFINE_TLS(CPUState *, current_cpu);
/* 0 = Do not count executed instructions.
1 = Precise instruction counting.
2 = Adaptive rate instruction counting. */
@ -351,27 +351,26 @@ const VMStateDescription vmstate_cpu_common = {
CPUState *qemu_get_cpu(int index)
{
CPUArchState *env = first_cpu;
CPUState *cpu = NULL;
CPUState *cpu = first_cpu;
while (env) {
cpu = ENV_GET_CPU(env);
while (cpu) {
if (cpu->cpu_index == index) {
break;
}
env = env->next_cpu;
cpu = cpu->next_cpu;
}
return env ? cpu : NULL;
return cpu;
}
void qemu_for_each_cpu(void (*func)(CPUState *cpu, void *data), void *data)
{
CPUArchState *env = first_cpu;
CPUState *cpu;
while (env) {
func(ENV_GET_CPU(env), data);
env = env->next_cpu;
cpu = first_cpu;
while (cpu) {
func(cpu, data);
cpu = cpu->next_cpu;
}
}
@ -379,17 +378,17 @@ void cpu_exec_init(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUArchState **penv;
CPUState **pcpu;
int cpu_index;
#if defined(CONFIG_USER_ONLY)
cpu_list_lock();
#endif
env->next_cpu = NULL;
penv = &first_cpu;
cpu->next_cpu = NULL;
pcpu = &first_cpu;
cpu_index = 0;
while (*penv != NULL) {
penv = &(*penv)->next_cpu;
while (*pcpu != NULL) {
pcpu = &(*pcpu)->next_cpu;
cpu_index++;
}
cpu->cpu_index = cpu_index;
@ -399,7 +398,7 @@ void cpu_exec_init(CPUArchState *env)
#ifndef CONFIG_USER_ONLY
cpu->thread_id = qemu_get_thread_id();
#endif
*penv = env;
*pcpu = cpu;
#if defined(CONFIG_USER_ONLY)
cpu_list_unlock();
#endif
@ -618,7 +617,7 @@ void cpu_abort(CPUArchState *env, const char *fmt, ...)
qemu_log("qemu: fatal: ");
qemu_log_vprintf(fmt, ap2);
qemu_log("\n");
log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
qemu_log_flush();
qemu_log_close();
}
@ -638,7 +637,6 @@ void cpu_abort(CPUArchState *env, const char *fmt, ...)
CPUArchState *cpu_copy(CPUArchState *env)
{
CPUArchState *new_env = cpu_init(env->cpu_model_str);
CPUArchState *next_cpu = new_env->next_cpu;
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
CPUWatchpoint *wp;
@ -646,9 +644,6 @@ CPUArchState *cpu_copy(CPUArchState *env)
memcpy(new_env, env, sizeof(CPUArchState));
/* Preserve chaining. */
new_env->next_cpu = next_cpu;
/* Clone all break/watchpoints.
Note: Once we support ptrace with hw-debug register access, make sure
BP_CPU break/watchpoints are handled correctly on clone. */
@ -1467,8 +1462,10 @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
/* we remove the notdirty callback only if the code has been
flushed */
if (dirty_flags == 0xff)
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
if (dirty_flags == 0xff) {
CPUArchState *env = current_cpu->env_ptr;
tlb_set_dirty(env, env->mem_io_vaddr);
}
}
static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
@ -1486,7 +1483,7 @@ static const MemoryRegionOps notdirty_mem_ops = {
/* Generate a debug exception if a watchpoint has been hit. */
static void check_watchpoint(int offset, int len_mask, int flags)
{
CPUArchState *env = cpu_single_env;
CPUArchState *env = current_cpu->env_ptr;
target_ulong pc, cs_base;
target_ulong vaddr;
CPUWatchpoint *wp;
@ -1750,12 +1747,14 @@ static void core_commit(MemoryListener *listener)
static void tcg_commit(MemoryListener *listener)
{
CPUArchState *env;
CPUState *cpu;
/* since each CPU stores ram addresses in its TLB cache, we must
reset the modified entries */
/* XXX: slow ! */
for(env = first_cpu; env != NULL; env = env->next_cpu) {
for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) {
CPUArchState *env = cpu->env_ptr;
tlb_flush(env, 1);
}
}
@ -1925,7 +1924,7 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
if (is_write) {
if (!memory_access_is_direct(mr, is_write)) {
l = memory_access_size(mr, l, addr1);
/* XXX: could force cpu_single_env to NULL to avoid
/* XXX: could force current_cpu to NULL to avoid
potential bugs */
if (l == 4) {
/* 32 bit write access */