mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 08:13:54 -06:00
hw/ssi: imx_spi: Disable chip selects when controller is disabled
When a write to ECSPI_CONREG register to disable the SPI controller,
imx_spi_soft_reset() is called to reset the controller, but chip
select lines should have been disabled, otherwise the state machine
of any devices (e.g.: SPI flashes) connected to the SPI master is
stuck to its last state and responds incorrectly to any follow-up
commands.
Fixes: c906a3a015
("i.MX: Add the Freescale SPI Controller")
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210129132323.30946-8-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
fb116b5456
commit
50dc25932e
1 changed files with 6 additions and 0 deletions
|
@ -254,9 +254,15 @@ static void imx_spi_common_reset(IMXSPIState *s)
|
||||||
|
|
||||||
static void imx_spi_soft_reset(IMXSPIState *s)
|
static void imx_spi_soft_reset(IMXSPIState *s)
|
||||||
{
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
imx_spi_common_reset(s);
|
imx_spi_common_reset(s);
|
||||||
|
|
||||||
imx_spi_update_irq(s);
|
imx_spi_update_irq(s);
|
||||||
|
|
||||||
|
for (i = 0; i < ECSPI_NUM_CS; i++) {
|
||||||
|
qemu_set_irq(s->cs_lines[i], 1);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void imx_spi_reset(DeviceState *dev)
|
static void imx_spi_reset(DeviceState *dev)
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue