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target/arm: Implement SVE2 fp multiply-add long

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Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-83-richard.henderson@linaro.org
Message-Id: <20200504171240.11220-1-steplong@quicinc.com>
[rth: Rearrange to use float16_to_float32_by_bits.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Stephen Long 2021-05-24 18:03:48 -07:00 • committed by Peter Maydell
parent 93966af1d3
commit 50d102bd42
4 changed files with 141 additions and 0 deletions
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75
target/arm/translate-sve.c
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@ -8535,3 +8535,78 @@ static bool trans_FLOGB(DisasContext *s, arg_rpr_esz *a)
}
return true;
}
static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
{
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
vec_full_reg_offset(s, a->ra),
cpu_env, vsz, vsz, (sel << 1) | sub,
gen_helper_sve2_fmlal_zzzw_s);
}
return true;
}
static bool trans_FMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_FMLAL_zzzw(s, a, false, false);
}
static bool trans_FMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_FMLAL_zzzw(s, a, false, true);
}
static bool trans_FMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_FMLAL_zzzw(s, a, true, false);
}
static bool trans_FMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_FMLAL_zzzw(s, a, true, true);
}
static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sub, bool sel)
{
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
vec_full_reg_offset(s, a->ra),
cpu_env, vsz, vsz,
(a->index << 2) | (sel << 1) | sub,
gen_helper_sve2_fmlal_zzxw_s);
}
return true;
}
static bool trans_FMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a)
{
return do_FMLAL_zzxw(s, a, false, false);
}
static bool trans_FMLALT_zzxw(DisasContext *s, arg_rrxr_esz *a)
{
return do_FMLAL_zzxw(s, a, false, true);
}
static bool trans_FMLSLB_zzxw(DisasContext *s, arg_rrxr_esz *a)
{
return do_FMLAL_zzxw(s, a, true, false);
}
static bool trans_FMLSLT_zzxw(DisasContext *s, arg_rrxr_esz *a)
{
return do_FMLAL_zzxw(s, a, true, true);
}