mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-07 17:53:56 -06:00
target/ppc: add external PID support
External PID is a mechanism present on BookE 2.06 that enables application to store/load data from different address spaces. There are special version of some instructions, which operate on alternate address space, which is specified in the EPLC/EPSC regiser. This implementation uses two additional MMU modes (mmu_idx) to provide the address space for the load and store instructions. The QEMU TLB fill code was modified to recognize these MMU modes and use the values in EPLC/EPSC to find the proper entry in he PPC TLB. These two QEMU TLBs are also flushed on each write to EPLC/EPSC. Following instructions are implemented: dcbfep dcbstep dcbtep dcbtstep dcbzep dcbzlep icbiep lbepx ldepx lfdepx lhepx lwepx stbepx stdepx stfdepx sthepx stwepx. Following vector instructions are not: evlddepx evstddepx lvepx lvepxl stvepx stvepxl. Signed-off-by: Roman Kapl <rka@sysgo.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Roman Kapl
David Gibson
parent
4de6bb0c02
commit
50728199c5
8 changed files with 387 additions and 45 deletions
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@ -924,29 +924,84 @@ static int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
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return 0;
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}
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static bool is_epid_mmu(int mmu_idx)
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{
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return mmu_idx == PPC_TLB_EPID_STORE || mmu_idx == PPC_TLB_EPID_LOAD;
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}
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static uint32_t mmubooke206_esr(int mmu_idx, bool rw)
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{
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uint32_t esr = 0;
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if (rw) {
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esr |= ESR_ST;
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}
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if (is_epid_mmu(mmu_idx)) {
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esr |= ESR_EPID;
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}
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return esr;
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}
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/* Get EPID register given the mmu_idx. If this is regular load,
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* construct the EPID access bits from current processor state */
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/* Get the effective AS and PR bits and the PID. The PID is returned only if
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* EPID load is requested, otherwise the caller must detect the correct EPID.
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* Return true if valid EPID is returned. */
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static bool mmubooke206_get_as(CPUPPCState *env,
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int mmu_idx, uint32_t *epid_out,
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bool *as_out, bool *pr_out)
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{
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if (is_epid_mmu(mmu_idx)) {
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uint32_t epidr;
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if (mmu_idx == PPC_TLB_EPID_STORE) {
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epidr = env->spr[SPR_BOOKE_EPSC];
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} else {
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epidr = env->spr[SPR_BOOKE_EPLC];
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}
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*epid_out = (epidr & EPID_EPID) >> EPID_EPID_SHIFT;
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*as_out = !!(epidr & EPID_EAS);
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*pr_out = !!(epidr & EPID_EPR);
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return true;
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} else {
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*as_out = msr_ds;
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*pr_out = msr_pr;
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return false;
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}
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}
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/* Check if the tlb found by hashing really matches */
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static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
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hwaddr *raddr, int *prot,
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target_ulong address, int rw,
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int access_type)
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int access_type, int mmu_idx)
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{
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int ret;
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int prot2 = 0;
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uint32_t epid;
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bool as, pr;
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bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
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if (ppcmas_tlb_check(env, tlb, raddr, address,
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env->spr[SPR_BOOKE_PID]) >= 0) {
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goto found_tlb;
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}
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if (!use_epid) {
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if (ppcmas_tlb_check(env, tlb, raddr, address,
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env->spr[SPR_BOOKE_PID]) >= 0) {
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goto found_tlb;
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}
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if (env->spr[SPR_BOOKE_PID1] &&
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ppcmas_tlb_check(env, tlb, raddr, address,
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env->spr[SPR_BOOKE_PID1]) >= 0) {
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goto found_tlb;
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}
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if (env->spr[SPR_BOOKE_PID1] &&
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ppcmas_tlb_check(env, tlb, raddr, address,
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env->spr[SPR_BOOKE_PID1]) >= 0) {
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goto found_tlb;
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}
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if (env->spr[SPR_BOOKE_PID2] &&
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ppcmas_tlb_check(env, tlb, raddr, address,
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env->spr[SPR_BOOKE_PID2]) >= 0) {
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goto found_tlb;
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if (env->spr[SPR_BOOKE_PID2] &&
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ppcmas_tlb_check(env, tlb, raddr, address,
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env->spr[SPR_BOOKE_PID2]) >= 0) {
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goto found_tlb;
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}
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} else {
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if (ppcmas_tlb_check(env, tlb, raddr, address, epid) >= 0) {
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goto found_tlb;
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}
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}
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LOG_SWTLB("%s: TLB entry not found\n", __func__);
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@ -954,7 +1009,7 @@ static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
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found_tlb:
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if (msr_pr != 0) {
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if (pr) {
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if (tlb->mas7_3 & MAS3_UR) {
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prot2 |= PAGE_READ;
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}
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@ -978,6 +1033,8 @@ found_tlb:
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/* Check the address space and permissions */
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if (access_type == ACCESS_CODE) {
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/* There is no way to fetch code using epid load */
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assert(!use_epid);
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if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
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LOG_SWTLB("%s: AS doesn't match\n", __func__);
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return -1;
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@ -992,7 +1049,7 @@ found_tlb:
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LOG_SWTLB("%s: no PAGE_EXEC: %x\n", __func__, prot2);
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ret = -3;
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} else {
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if (msr_dr != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
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if (as != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
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LOG_SWTLB("%s: AS doesn't match\n", __func__);
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return -1;
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}
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@ -1012,7 +1069,7 @@ found_tlb:
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static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong address, int rw,
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int access_type)
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int access_type, int mmu_idx)
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{
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ppcmas_tlb_t *tlb;
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hwaddr raddr;
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@ -1030,7 +1087,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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continue;
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}
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ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address,
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rw, access_type);
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rw, access_type, mmu_idx);
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if (ret != -1) {
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goto found_tlb;
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}
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@ -1348,8 +1405,10 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
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return ret;
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}
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static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int access_type)
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static int get_physical_address_wtlb(
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CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int access_type,
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int mmu_idx)
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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int ret = -1;
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@ -1392,7 +1451,7 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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break;
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case POWERPC_MMU_BOOKE206:
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ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
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access_type);
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access_type, mmu_idx);
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break;
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case POWERPC_MMU_MPC8xx:
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/* XXX: TODO */
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@ -1417,6 +1476,13 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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return ret;
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}
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static int get_physical_address(
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CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int access_type)
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{
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return get_physical_address_wtlb(env, ctx, eaddr, rw, access_type, 0);
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}
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hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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@ -1463,8 +1529,15 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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}
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static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
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int rw)
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int rw, int mmu_idx)
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{
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uint32_t epid;
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bool as, pr;
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uint32_t missed_tid = 0;
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bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
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if (rw == 2) {
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as = msr_ir;
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}
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env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK;
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env->spr[SPR_BOOKE_MAS1] = env->spr[SPR_BOOKE_MAS4] & MAS4_TSIZED_MASK;
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env->spr[SPR_BOOKE_MAS2] = env->spr[SPR_BOOKE_MAS4] & MAS4_WIMGED_MASK;
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@ -1473,7 +1546,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
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env->spr[SPR_BOOKE_MAS7] = 0;
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/* AS */
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if (((rw == 2) && msr_ir) || ((rw != 2) && msr_dr)) {
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if (as) {
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env->spr[SPR_BOOKE_MAS1] |= MAS1_TS;
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env->spr[SPR_BOOKE_MAS6] |= MAS6_SAS;
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}
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@ -1481,19 +1554,25 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
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env->spr[SPR_BOOKE_MAS1] |= MAS1_VALID;
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env->spr[SPR_BOOKE_MAS2] |= address & MAS2_EPN_MASK;
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switch (env->spr[SPR_BOOKE_MAS4] & MAS4_TIDSELD_PIDZ) {
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case MAS4_TIDSELD_PID0:
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env->spr[SPR_BOOKE_MAS1] |= env->spr[SPR_BOOKE_PID] << MAS1_TID_SHIFT;
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break;
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case MAS4_TIDSELD_PID1:
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env->spr[SPR_BOOKE_MAS1] |= env->spr[SPR_BOOKE_PID1] << MAS1_TID_SHIFT;
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break;
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case MAS4_TIDSELD_PID2:
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env->spr[SPR_BOOKE_MAS1] |= env->spr[SPR_BOOKE_PID2] << MAS1_TID_SHIFT;
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break;
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if (!use_epid) {
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switch (env->spr[SPR_BOOKE_MAS4] & MAS4_TIDSELD_PIDZ) {
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case MAS4_TIDSELD_PID0:
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missed_tid = env->spr[SPR_BOOKE_PID];
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break;
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case MAS4_TIDSELD_PID1:
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missed_tid = env->spr[SPR_BOOKE_PID1];
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break;
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case MAS4_TIDSELD_PID2:
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missed_tid = env->spr[SPR_BOOKE_PID2];
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break;
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}
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env->spr[SPR_BOOKE_MAS6] |= env->spr[SPR_BOOKE_PID] << 16;
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} else {
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missed_tid = epid;
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env->spr[SPR_BOOKE_MAS6] |= missed_tid << 16;
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}
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env->spr[SPR_BOOKE_MAS1] |= (missed_tid << MAS1_TID_SHIFT);
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env->spr[SPR_BOOKE_MAS6] |= env->spr[SPR_BOOKE_PID] << 16;
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/* next victim logic */
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env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_ESEL_SHIFT;
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@ -1520,7 +1599,8 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
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/* data access */
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access_type = env->access_type;
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}
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ret = get_physical_address(env, &ctx, address, rw, access_type);
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ret = get_physical_address_wtlb(env, &ctx, address, rw,
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access_type, mmu_idx);
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if (ret == 0) {
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
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@ -1550,12 +1630,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
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env->spr[SPR_40x_ESR] = 0x00000000;
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break;
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case POWERPC_MMU_BOOKE206:
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booke206_update_mas_tlb_miss(env, address, 2);
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booke206_update_mas_tlb_miss(env, address, 2, mmu_idx);
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/* fall through */
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case POWERPC_MMU_BOOKE:
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cs->exception_index = POWERPC_EXCP_ITLB;
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env->error_code = 0;
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env->spr[SPR_BOOKE_DEAR] = address;
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env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, 0);
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return -1;
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case POWERPC_MMU_MPC8xx:
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/* XXX: TODO */
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@ -1642,13 +1723,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
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cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
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break;
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case POWERPC_MMU_BOOKE206:
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booke206_update_mas_tlb_miss(env, address, rw);
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booke206_update_mas_tlb_miss(env, address, rw, mmu_idx);
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/* fall through */
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case POWERPC_MMU_BOOKE:
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cs->exception_index = POWERPC_EXCP_DTLB;
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env->error_code = 0;
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env->spr[SPR_BOOKE_DEAR] = address;
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env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
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env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, rw);
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return -1;
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case POWERPC_MMU_REAL:
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cpu_abort(cs, "PowerPC in real mode should never raise "
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@ -1672,7 +1753,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
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} else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
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(env->mmu_model == POWERPC_MMU_BOOKE206)) {
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env->spr[SPR_BOOKE_DEAR] = address;
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env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
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env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, rw);
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} else {
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env->spr[SPR_DAR] = address;
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if (rw == 1) {
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@ -2598,6 +2679,19 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
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tlb_flush(CPU(cpu));
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}
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void helper_booke_set_eplc(CPUPPCState *env, target_ulong val)
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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env->spr[SPR_BOOKE_EPLC] = val & EPID_MASK;
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tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_LOAD);
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}
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void helper_booke_set_epsc(CPUPPCState *env, target_ulong val)
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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env->spr[SPR_BOOKE_EPSC] = val & EPID_MASK;
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tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_STORE);
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}
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static inline void flush_page(CPUPPCState *env, ppcmas_tlb_t *tlb)
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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