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target/arm: Convert RBIT, REV16, REV32, REV64 to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:29:34 -06:00 • committed by Peter Maydell
parent b466ea8f21
commit 506a8c11e7
2 changed files with 72 additions and 76 deletions
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11
target/arm/tcg/a64.decode
View file

@ -28,6 +28,8 @@
&r rn
&rrr rd rn rm
&ri rd imm
&rr rd rn
&rr_sf rd rn sf
&rri_sf rd rn imm sf
&rrr_sf rd rn rm sf
&i imm
@ -685,6 +687,15 @@ GMI 1 00 11010110 ..... 000101 ..... ..... @rrr
PACGA 1 00 11010110 ..... 001100 ..... ..... @rrr
# Data Processing (1-source)
@rr . .......... ..... ...... rn:5 rd:5 &rr
@rr_sf sf:1 .......... ..... ...... rn:5 rd:5 &rr_sf
RBIT . 10 11010110 00000 000000 ..... ..... @rr_sf
REV16 . 10 11010110 00000 000001 ..... ..... @rr_sf
REV32 . 10 11010110 00000 000010 ..... ..... @rr_sf
REV64 1 10 11010110 00000 000011 ..... ..... @rr
# Logical (shifted reg)
# Add/subtract (shifted reg)
# Add/subtract (extended reg)

137
target/arm/tcg/translate-a64.c
View file

@ -7684,6 +7684,60 @@ static bool trans_PACGA(DisasContext *s, arg_rrr *a)
return false;
}
typedef void ArithOneOp(TCGv_i64, TCGv_i64);
static bool gen_rr(DisasContext *s, int rd, int rn, ArithOneOp fn)
{
fn(cpu_reg(s, rd), cpu_reg(s, rn));
return true;
}
static void gen_rbit32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
TCGv_i32 t32 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t32, tcg_rn);
gen_helper_rbit(t32, t32);
tcg_gen_extu_i32_i64(tcg_rd, t32);
}
static void gen_rev16_xx(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 mask)
{
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask);
tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
}
static void gen_rev16_32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
gen_rev16_xx(tcg_rd, tcg_rn, tcg_constant_i64(0x00ff00ff));
}
static void gen_rev16_64(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
gen_rev16_xx(tcg_rd, tcg_rn, tcg_constant_i64(0x00ff00ff00ff00ffull));
}
static void gen_rev_32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
tcg_gen_bswap32_i64(tcg_rd, tcg_rn, TCG_BSWAP_OZ);
}
static void gen_rev32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
{
tcg_gen_bswap64_i64(tcg_rd, tcg_rn);
tcg_gen_rotri_i64(tcg_rd, tcg_rd, 32);
}
TRANS(RBIT, gen_rr, a->rd, a->rn, a->sf ? gen_helper_rbit64 : gen_rbit32)
TRANS(REV16, gen_rr, a->rd, a->rn, a->sf ? gen_rev16_64 : gen_rev16_32)
TRANS(REV32, gen_rr, a->rd, a->rn, a->sf ? gen_rev32 : gen_rev_32)
TRANS(REV64, gen_rr, a->rd, a->rn, tcg_gen_bswap64_i64)
/* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
@ -8302,67 +8356,6 @@ static void handle_cls(DisasContext *s, unsigned int sf,
}
}
static void handle_rbit(DisasContext *s, unsigned int sf,
unsigned int rn, unsigned int rd)
{
TCGv_i64 tcg_rd, tcg_rn;
tcg_rd = cpu_reg(s, rd);
tcg_rn = cpu_reg(s, rn);
if (sf) {
gen_helper_rbit64(tcg_rd, tcg_rn);
} else {
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
gen_helper_rbit(tcg_tmp32, tcg_tmp32);
tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
}
}
/* REV with sf==1, opcode==3 ("REV64") */
static void handle_rev64(DisasContext *s, unsigned int sf,
unsigned int rn, unsigned int rd)
{
if (!sf) {
unallocated_encoding(s);
return;
}
tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
}
/* REV with sf==0, opcode==2
* REV32 (sf==1, opcode==2)
*/
static void handle_rev32(DisasContext *s, unsigned int sf,
unsigned int rn, unsigned int rd)
{
TCGv_i64 tcg_rd = cpu_reg(s, rd);
TCGv_i64 tcg_rn = cpu_reg(s, rn);
if (sf) {
tcg_gen_bswap64_i64(tcg_rd, tcg_rn);
tcg_gen_rotri_i64(tcg_rd, tcg_rd, 32);
} else {
tcg_gen_bswap32_i64(tcg_rd, tcg_rn, TCG_BSWAP_OZ);
}
}
/* REV16 (opcode==1) */
static void handle_rev16(DisasContext *s, unsigned int sf,
unsigned int rn, unsigned int rd)
{
TCGv_i64 tcg_rd = cpu_reg(s, rd);
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
TCGv_i64 mask = tcg_constant_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask);
tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
}
/* Data-processing (1 source)
* 31 30 29 28 21 20 16 15 10 9 5 4 0
* +----+---+---+-----------------+---------+--------+------+------+
@ -8388,21 +8381,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
#define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
switch (MAP(sf, opcode2, opcode)) {
case MAP(0, 0x00, 0x00): /* RBIT */
case MAP(1, 0x00, 0x00):
handle_rbit(s, sf, rn, rd);
break;
case MAP(0, 0x00, 0x01): /* REV16 */
case MAP(1, 0x00, 0x01):
handle_rev16(s, sf, rn, rd);
break;
case MAP(0, 0x00, 0x02): /* REV/REV32 */
case MAP(1, 0x00, 0x02):
handle_rev32(s, sf, rn, rd);
break;
case MAP(1, 0x00, 0x03): /* REV64 */
handle_rev64(s, sf, rn, rd);
break;
case MAP(0, 0x00, 0x04): /* CLZ */
case MAP(1, 0x00, 0x04):
handle_clz(s, sf, rn, rd);
@ -8557,6 +8535,13 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
break;
default:
do_unallocated:
case MAP(0, 0x00, 0x00): /* RBIT */
case MAP(1, 0x00, 0x00):
case MAP(0, 0x00, 0x01): /* REV16 */
case MAP(1, 0x00, 0x01):
case MAP(0, 0x00, 0x02): /* REV/REV32 */
case MAP(1, 0x00, 0x02):
case MAP(1, 0x00, 0x03): /* REV64 */
unallocated_encoding(s);
break;
}