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target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv

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The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
whether ISI and DSI interrupts were directed to the hypervisor or the
partition. These interrupts now go to the hypervisor irrespective, thus
it is no longer necessary to check the vmp0 bit in the LPCR.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Suraj Jitindar Singh 2017-02-10 16:25:54 +11:00 • committed by David Gibson
parent 18aa49ecf4
commit 5065908361
1 changed files with 18 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

20
target/ppc/mmu-hash64.c
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@ -652,7 +652,15 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
if (msr_ir) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
switch (env->mmu_model) {
case POWERPC_MMU_3_00:
/* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
vpm = true;
break;
default:
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
break;
}
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HISI;
@ -670,7 +678,15 @@ static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
if (msr_dr) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
switch (env->mmu_model) {
case POWERPC_MMU_3_00:
/* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
vpm = true;
break;
default:
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
break;
}
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HDSI;