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Rearrange PCI host emulation code.
Add ARM PCI emulation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1916 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook
parent
4aa4253115
commit
502a53952d
19 changed files with 1750 additions and 1441 deletions
419
hw/piix_pci.c
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419
hw/piix_pci.c
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@ -0,0 +1,419 @@
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/*
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* QEMU i440FX/PIIX3 PCI Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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typedef uint32_t pci_addr_t;
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#include "pci_host.h"
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typedef PCIHostState I440FXState;
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static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
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{
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I440FXState *s = opaque;
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s->config_reg = val;
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}
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static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
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{
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I440FXState *s = opaque;
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return s->config_reg;
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}
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static void piix3_set_irq(PCIDevice *pci_dev, void *pic, int irq_num, int level);
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PCIBus *i440fx_init(void)
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{
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PCIBus *b;
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PCIDevice *d;
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I440FXState *s;
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s = qemu_mallocz(sizeof(I440FXState));
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b = pci_register_bus(piix3_set_irq, NULL, 0);
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s->bus = b;
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register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
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register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
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register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
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register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
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register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
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register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
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register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
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register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
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d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
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NULL, NULL);
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d->config[0x00] = 0x86; // vendor_id
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d->config[0x01] = 0x80;
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d->config[0x02] = 0x37; // device_id
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d->config[0x03] = 0x12;
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d->config[0x08] = 0x02; // revision
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d->config[0x0a] = 0x00; // class_sub = host2pci
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0e] = 0x00; // header_type
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return b;
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}
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/* PIIX3 PCI to ISA bridge */
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static PCIDevice *piix3_dev;
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/* just used for simpler irq handling. */
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#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
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static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
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/* return the global irq number corresponding to a given device irq
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pin. We could also use the bus number to have a more precise
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mapping. */
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static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
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{
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int slot_addend;
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slot_addend = (pci_dev->devfn >> 3) - 1;
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return (irq_num + slot_addend) & 3;
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}
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static inline int get_pci_irq_level(int irq_num)
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{
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int pic_level;
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#if (PCI_IRQ_WORDS == 2)
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pic_level = ((pci_irq_levels[irq_num][0] |
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pci_irq_levels[irq_num][1]) != 0);
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#else
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{
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int i;
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pic_level = 0;
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for(i = 0; i < PCI_IRQ_WORDS; i++) {
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if (pci_irq_levels[irq_num][i]) {
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pic_level = 1;
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break;
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}
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}
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}
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#endif
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return pic_level;
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}
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static void piix3_set_irq(PCIDevice *pci_dev, void *pic, int irq_num, int level)
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{
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int irq_index, shift, pic_irq, pic_level;
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uint32_t *p;
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irq_num = pci_slot_get_pirq(pci_dev, irq_num);
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irq_index = pci_dev->irq_index;
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p = &pci_irq_levels[irq_num][irq_index >> 5];
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shift = (irq_index & 0x1f);
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*p = (*p & ~(1 << shift)) | (level << shift);
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/* now we change the pic irq level according to the piix irq mappings */
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/* XXX: optimize */
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pic_irq = piix3_dev->config[0x60 + irq_num];
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if (pic_irq < 16) {
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/* the pic level is the logical OR of all the PCI irqs mapped
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to it */
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pic_level = 0;
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if (pic_irq == piix3_dev->config[0x60])
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pic_level |= get_pci_irq_level(0);
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if (pic_irq == piix3_dev->config[0x61])
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pic_level |= get_pci_irq_level(1);
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if (pic_irq == piix3_dev->config[0x62])
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pic_level |= get_pci_irq_level(2);
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if (pic_irq == piix3_dev->config[0x63])
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pic_level |= get_pci_irq_level(3);
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pic_set_irq(pic_irq, pic_level);
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}
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}
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static void piix3_reset(PCIDevice *d)
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{
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uint8_t *pci_conf = d->config;
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pci_conf[0x04] = 0x07; // master, memory and I/O
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pci_conf[0x05] = 0x00;
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pci_conf[0x06] = 0x00;
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pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
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pci_conf[0x4c] = 0x4d;
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pci_conf[0x4e] = 0x03;
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pci_conf[0x4f] = 0x00;
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pci_conf[0x60] = 0x80;
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pci_conf[0x69] = 0x02;
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pci_conf[0x70] = 0x80;
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pci_conf[0x76] = 0x0c;
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pci_conf[0x77] = 0x0c;
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pci_conf[0x78] = 0x02;
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pci_conf[0x79] = 0x00;
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pci_conf[0x80] = 0x00;
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pci_conf[0x82] = 0x00;
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pci_conf[0xa0] = 0x08;
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pci_conf[0xa0] = 0x08;
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pci_conf[0xa2] = 0x00;
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pci_conf[0xa3] = 0x00;
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pci_conf[0xa4] = 0x00;
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pci_conf[0xa5] = 0x00;
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pci_conf[0xa6] = 0x00;
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pci_conf[0xa7] = 0x00;
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pci_conf[0xa8] = 0x0f;
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pci_conf[0xaa] = 0x00;
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pci_conf[0xab] = 0x00;
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pci_conf[0xac] = 0x00;
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pci_conf[0xae] = 0x00;
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}
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int piix3_init(PCIBus *bus)
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{
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PCIDevice *d;
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uint8_t *pci_conf;
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d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice),
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-1, NULL, NULL);
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register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d);
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piix3_dev = d;
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pci_conf = d->config;
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pci_conf[0x00] = 0x86; // Intel
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pci_conf[0x01] = 0x80;
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pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
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pci_conf[0x03] = 0x70;
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pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
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pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
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pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
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piix3_reset(d);
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return d->devfn;
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}
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/***********************************************************/
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/* XXX: the following should be moved to the PC BIOS */
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static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
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{
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return cpu_inb(NULL, addr);
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}
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static void isa_outb(uint32_t val, uint32_t addr)
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{
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cpu_outb(NULL, addr, val);
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}
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static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
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{
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return cpu_inw(NULL, addr);
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}
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static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
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{
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cpu_outw(NULL, addr, val);
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}
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static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
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{
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return cpu_inl(NULL, addr);
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}
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static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
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{
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cpu_outl(NULL, addr, val);
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}
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static uint32_t pci_bios_io_addr;
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static uint32_t pci_bios_mem_addr;
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/* host irqs corresponding to PCI irqs A-D */
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static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
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static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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pci_data_write(s, addr, val, 4);
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}
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static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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pci_data_write(s, addr, val, 2);
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}
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static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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pci_data_write(s, addr, val, 1);
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}
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static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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return pci_data_read(s, addr, 4);
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}
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static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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return pci_data_read(s, addr, 2);
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}
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static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
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{
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PCIBus *s = d->bus;
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addr |= (pci_bus_num(s) << 16) | (d->devfn << 8);
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return pci_data_read(s, addr, 1);
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}
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static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
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{
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PCIIORegion *r;
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uint16_t cmd;
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uint32_t ofs;
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if ( region_num == PCI_ROM_SLOT ) {
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ofs = 0x30;
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}else{
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ofs = 0x10 + region_num * 4;
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}
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pci_config_writel(d, ofs, addr);
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r = &d->io_regions[region_num];
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/* enable memory mappings */
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cmd = pci_config_readw(d, PCI_COMMAND);
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if ( region_num == PCI_ROM_SLOT )
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cmd |= 2;
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else if (r->type & PCI_ADDRESS_SPACE_IO)
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cmd |= 1;
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else
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cmd |= 2;
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pci_config_writew(d, PCI_COMMAND, cmd);
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}
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static void pci_bios_init_device(PCIDevice *d)
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{
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int class;
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PCIIORegion *r;
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uint32_t *paddr;
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int i, pin, pic_irq, vendor_id, device_id;
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class = pci_config_readw(d, PCI_CLASS_DEVICE);
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vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
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device_id = pci_config_readw(d, PCI_DEVICE_ID);
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switch(class) {
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case 0x0101:
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if (vendor_id == 0x8086 && device_id == 0x7010) {
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/* PIIX3 IDE */
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pci_config_writew(d, 0x40, 0x8000); // enable IDE0
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pci_config_writew(d, 0x42, 0x8000); // enable IDE1
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goto default_map;
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} else {
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/* IDE: we map it as in ISA mode */
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pci_set_io_region_addr(d, 0, 0x1f0);
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pci_set_io_region_addr(d, 1, 0x3f4);
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pci_set_io_region_addr(d, 2, 0x170);
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pci_set_io_region_addr(d, 3, 0x374);
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}
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break;
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case 0x0300:
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if (vendor_id != 0x1234)
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goto default_map;
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/* VGA: map frame buffer to default Bochs VBE address */
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pci_set_io_region_addr(d, 0, 0xE0000000);
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break;
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case 0x0800:
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/* PIC */
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vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
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device_id = pci_config_readw(d, PCI_DEVICE_ID);
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if (vendor_id == 0x1014) {
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/* IBM */
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if (device_id == 0x0046 || device_id == 0xFFFF) {
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/* MPIC & MPIC2 */
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pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
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}
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}
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break;
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case 0xff00:
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if (vendor_id == 0x0106b &&
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(device_id == 0x0017 || device_id == 0x0022)) {
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/* macio bridge */
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pci_set_io_region_addr(d, 0, 0x80800000);
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}
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break;
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default:
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default_map:
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/* default memory mappings */
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for(i = 0; i < PCI_NUM_REGIONS; i++) {
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r = &d->io_regions[i];
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if (r->size) {
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if (r->type & PCI_ADDRESS_SPACE_IO)
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paddr = &pci_bios_io_addr;
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else
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paddr = &pci_bios_mem_addr;
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*paddr = (*paddr + r->size - 1) & ~(r->size - 1);
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pci_set_io_region_addr(d, i, *paddr);
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*paddr += r->size;
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}
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}
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break;
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}
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/* map the interrupt */
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pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
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if (pin != 0) {
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pin = pci_slot_get_pirq(d, pin - 1);
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pic_irq = pci_irqs[pin];
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pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
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}
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}
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/*
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* This function initializes the PCI devices as a normal PCI BIOS
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* would do. It is provided just in case the BIOS has no support for
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* PCI.
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*/
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void pci_bios_init(void)
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{
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int i, irq;
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uint8_t elcr[2];
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pci_bios_io_addr = 0xc000;
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pci_bios_mem_addr = 0xf0000000;
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/* activate IRQ mappings */
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elcr[0] = 0x00;
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elcr[1] = 0x00;
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for(i = 0; i < 4; i++) {
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irq = pci_irqs[i];
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/* set to trigger level */
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elcr[irq >> 3] |= (1 << (irq & 7));
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/* activate irq remapping in PIIX */
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pci_config_writeb(piix3_dev, 0x60 + i, irq);
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}
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isa_outb(elcr[0], 0x4d0);
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isa_outb(elcr[1], 0x4d1);
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pci_for_each_device(pci_bios_init_device);
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}
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