motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-03 07:43:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer

Browse source 
This simple mux sits between the PLL channels and the DSI0E and DSI0P
clock muxes. This mux selects between PLLA-DSI0 and PLLD-DSI0 channel
and outputs the selected signal to source number 4 of DSI0E/P clock
muxes. It is controlled by the cm_dsi0hsck register.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel 2020-10-10 15:57:56 +02:00 • committed by Peter Maydell
parent fc9840850b
commit 502960ca04
3 changed files with 94 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

15
include/hw/misc/bcm2835_cprman.h
View file

@ -174,6 +174,20 @@ typedef struct CprmanClockMuxState {
struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC];
} CprmanClockMuxState;
typedef struct CprmanDsi0HsckMuxState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
CprmanClockMux id;
uint32_t *reg_cm;
Clock *plla_in;
Clock *plld_in;
Clock *out;
} CprmanDsi0HsckMuxState;
struct BCM2835CprmanState {
/*< private >*/
SysBusDevice parent_obj;
@ -184,6 +198,7 @@ struct BCM2835CprmanState {
CprmanPllState plls[CPRMAN_NUM_PLL];
CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX];
CprmanDsi0HsckMuxState dsi0hsck_mux;
uint32_t regs[CPRMAN_NUM_REGS];
uint32_t xosc_freq;

6
include/hw/misc/bcm2835_cprman_internals.h
View file

@ -15,6 +15,7 @@
#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
#define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
#define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux"
DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
TYPE_CPRMAN_PLL)
@ -22,6 +23,8 @@ DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PLL_CHANNEL,
TYPE_CPRMAN_PLL_CHANNEL)
DECLARE_INSTANCE_CHECKER(CprmanClockMuxState, CPRMAN_CLOCK_MUX,
TYPE_CPRMAN_CLOCK_MUX)
DECLARE_INSTANCE_CHECKER(CprmanDsi0HsckMuxState, CPRMAN_DSI0HSCK_MUX,
TYPE_CPRMAN_DSI0HSCK_MUX)
/* Register map */
@ -223,6 +226,9 @@ REG32(CM_LOCK, 0x114)
FIELD(CM_LOCK, FLOCKB, 9, 1)
FIELD(CM_LOCK, FLOCKA, 8, 1)
REG32(CM_DSI0HSCK, 0x120)
FIELD(CM_DSI0HSCK, SELPLLD, 0, 1)
/*
* This field is common to all registers. Each register write value must match
* the CPRMAN_PASSWORD magic value in its 8 MSB.