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target/riscv: Add support to record CTR entries.
This commit adds logic to records CTR entries of different types and adds required hooks in TCG and interrupt/Exception logic to record events. This commit also adds support to invoke freeze CTR logic for breakpoint exceptions and counter overflow interrupts. Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250205-b4-ctr_upstream_v6-v6-4-439d8e06c8ef@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Rajnesh Kanwal
Alistair Francis
parent
c48bd18eae
commit
4ff7a27adc
8 changed files with 430 additions and 0 deletions
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@ -875,6 +875,247 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
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}
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}
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static void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask,
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bool virt)
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{
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uint64_t ctl = virt ? env->vsctrctl : env->mctrctl;
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assert((freeze_mask & (~(XCTRCTL_BPFRZ | XCTRCTL_LCOFIFRZ))) == 0);
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if (ctl & freeze_mask) {
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env->sctrstatus |= SCTRSTATUS_FROZEN;
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}
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}
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static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt)
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{
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switch (priv) {
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case PRV_M:
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return MCTRCTL_M;
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case PRV_S:
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if (virt) {
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return XCTRCTL_S;
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}
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return XCTRCTL_S;
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case PRV_U:
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if (virt) {
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return XCTRCTL_U;
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}
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return XCTRCTL_U;
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}
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g_assert_not_reached();
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}
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static uint64_t riscv_ctr_get_control(CPURISCVState *env, target_long priv,
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bool virt)
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{
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switch (priv) {
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case PRV_M:
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return env->mctrctl;
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case PRV_S:
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case PRV_U:
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if (virt) {
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return env->vsctrctl;
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}
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return env->mctrctl;
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}
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g_assert_not_reached();
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}
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/*
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* This function assumes that src privilege and target privilege are not same
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* and src privilege is less than target privilege. This includes the virtual
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* state as well.
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*/
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static bool riscv_ctr_check_xte(CPURISCVState *env, target_long src_prv,
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bool src_virt)
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{
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target_long tgt_prv = env->priv;
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bool res = true;
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/*
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* VS and U mode are same in terms of xTE bits required to record an
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* external trap. See 6.1.2. External Traps, table 8 External Trap Enable
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* Requirements. This changes VS to U to simplify the logic a bit.
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*/
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if (src_virt && src_prv == PRV_S) {
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src_prv = PRV_U;
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} else if (env->virt_enabled && tgt_prv == PRV_S) {
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tgt_prv = PRV_U;
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}
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/* VU mode is an outlier here. */
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if (src_virt && src_prv == PRV_U) {
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res &= !!(env->vsctrctl & XCTRCTL_STE);
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}
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switch (src_prv) {
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case PRV_U:
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if (tgt_prv == PRV_U) {
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break;
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}
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res &= !!(env->mctrctl & XCTRCTL_STE);
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/* fall-through */
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case PRV_S:
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if (tgt_prv == PRV_S) {
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break;
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}
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res &= !!(env->mctrctl & MCTRCTL_MTE);
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/* fall-through */
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case PRV_M:
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break;
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}
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return res;
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}
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/*
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* Special cases for traps and trap returns:
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*
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* 1- Traps, and trap returns, between enabled modes are recorded as normal.
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* 2- Traps from an inhibited mode to an enabled mode, and trap returns from an
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* enabled mode back to an inhibited mode, are partially recorded. In such
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* cases, the PC from the inhibited mode (source PC for traps, and target PC
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* for trap returns) is 0.
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*
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* 3- Trap returns from an inhibited mode to an enabled mode are not recorded.
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* Traps from an enabled mode to an inhibited mode, known as external traps,
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* receive special handling.
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* By default external traps are not recorded, but a handshake mechanism exists
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* to allow partial recording. Software running in the target mode of the trap
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* can opt-in to allowing CTR to record traps into that mode even when the mode
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* is inhibited. The MTE, STE, and VSTE bits allow M-mode, S-mode, and VS-mode,
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* respectively, to opt-in. When an External Trap occurs, and xTE=1, such that
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* x is the target privilege mode of the trap, will CTR record the trap. In such
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* cases, the target PC is 0.
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*/
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/*
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* CTR arrays are implemented as circular buffers and new entry is stored at
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* sctrstatus.WRPTR, but they are presented to software as moving circular
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* buffers. Which means, software get's the illusion that whenever a new entry
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* is added the whole buffer is moved by one place and the new entry is added at
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* the start keeping new entry at idx 0 and older ones follow.
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*
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* Depth = 16.
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*
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* buffer [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
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* WRPTR W
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* entry 7 6 5 4 3 2 1 0 F E D C B A 9 8
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*
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* When a new entry is added:
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* buffer [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
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* WRPTR W
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* entry 8 7 6 5 4 3 2 1 0 F E D C B A 9
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*
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* entry here denotes the logical entry number that software can access
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* using ctrsource, ctrtarget and ctrdata registers. So xiselect 0x200
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* will return entry 0 i-e buffer[8] and 0x201 will return entry 1 i-e
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* buffer[7]. Here is how we convert entry to buffer idx.
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*
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* entry = isel - CTR_ENTRIES_FIRST;
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* idx = (sctrstatus.WRPTR - entry - 1) & (depth - 1);
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*/
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void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst,
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enum CTRType type, target_ulong src_priv, bool src_virt)
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{
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bool tgt_virt = env->virt_enabled;
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uint64_t src_mask = riscv_ctr_priv_to_mask(src_priv, src_virt);
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uint64_t tgt_mask = riscv_ctr_priv_to_mask(env->priv, tgt_virt);
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uint64_t src_ctrl = riscv_ctr_get_control(env, src_priv, src_virt);
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uint64_t tgt_ctrl = riscv_ctr_get_control(env, env->priv, tgt_virt);
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uint64_t depth, head;
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bool ext_trap = false;
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/*
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* Return immediately if both target and src recording is disabled or if
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* CTR is in frozen state.
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*/
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if ((!(src_ctrl & src_mask) && !(tgt_ctrl & tgt_mask)) ||
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env->sctrstatus & SCTRSTATUS_FROZEN) {
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return;
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}
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/*
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* With RAS Emul enabled, only allow Indirect, direct calls, Function
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* returns and Co-routine swap types.
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*/
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if (tgt_ctrl & XCTRCTL_RASEMU &&
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type != CTRDATA_TYPE_INDIRECT_CALL &&
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type != CTRDATA_TYPE_DIRECT_CALL &&
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type != CTRDATA_TYPE_RETURN &&
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type != CTRDATA_TYPE_CO_ROUTINE_SWAP) {
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return;
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}
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if (type == CTRDATA_TYPE_EXCEPTION || type == CTRDATA_TYPE_INTERRUPT) {
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/* Case 2 for traps. */
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if (!(src_ctrl & src_mask)) {
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src = 0;
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} else if (!(tgt_ctrl & tgt_mask)) {
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/* Check if target priv-mode has allowed external trap recording. */
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if (!riscv_ctr_check_xte(env, src_priv, src_virt)) {
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return;
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}
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ext_trap = true;
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dst = 0;
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}
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} else if (type == CTRDATA_TYPE_EXCEP_INT_RET) {
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/*
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* Case 3 for trap returns. Trap returns from inhibited mode are not
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* recorded.
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*/
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if (!(src_ctrl & src_mask)) {
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return;
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}
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/* Case 2 for trap returns. */
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if (!(tgt_ctrl & tgt_mask)) {
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dst = 0;
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}
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}
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/* Ignore filters in case of RASEMU mode or External trap. */
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if (!(tgt_ctrl & XCTRCTL_RASEMU) && !ext_trap) {
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/*
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* Check if the specific type is inhibited. Not taken branch filter is
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* an enable bit and needs to be checked separatly.
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*/
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bool check = tgt_ctrl & BIT_ULL(type + XCTRCTL_INH_START);
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if ((type == CTRDATA_TYPE_NONTAKEN_BRANCH && !check) ||
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(type != CTRDATA_TYPE_NONTAKEN_BRANCH && check)) {
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return;
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}
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}
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head = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
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depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
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if (tgt_ctrl & XCTRCTL_RASEMU && type == CTRDATA_TYPE_RETURN) {
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head = (head - 1) & (depth - 1);
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env->ctr_src[head] &= ~CTRSOURCE_VALID;
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env->sctrstatus =
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set_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK, head);
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return;
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}
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/* In case of Co-routine SWAP we overwrite latest entry. */
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if (tgt_ctrl & XCTRCTL_RASEMU && type == CTRDATA_TYPE_CO_ROUTINE_SWAP) {
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head = (head - 1) & (depth - 1);
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}
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env->ctr_src[head] = src | CTRSOURCE_VALID;
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env->ctr_dst[head] = dst & ~CTRTARGET_MISP;
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env->ctr_data[head] = set_field(0, CTRDATA_TYPE_MASK, type);
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head = (head + 1) & (depth - 1);
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env->sctrstatus = set_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK, head);
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}
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void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en)
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{
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g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED);
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@ -1993,10 +2234,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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!(env->mip & (1ULL << cause));
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bool smode_double_trap = false;
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uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
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const bool prev_virt = env->virt_enabled;
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const target_ulong prev_priv = env->priv;
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target_ulong tval = 0;
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target_ulong tinst = 0;
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target_ulong htval = 0;
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target_ulong mtval2 = 0;
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target_ulong src;
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int sxlen = 0;
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int mxlen = 16 << riscv_cpu_mxl(env);
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bool nnmi_excep = false;
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@ -2182,6 +2426,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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env->pc = (env->stvec >> 2 << 2) +
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((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
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riscv_cpu_set_mode(env, PRV_S, virt);
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src = env->sepc;
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} else {
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/*
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* If the hart encounters an exception while executing in M-mode
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@ -2266,6 +2512,19 @@ void riscv_cpu_do_interrupt(CPUState *cs)
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((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
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}
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riscv_cpu_set_mode(env, PRV_M, virt);
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src = env->mepc;
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}
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if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) {
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if (async && cause == IRQ_PMU_OVF) {
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riscv_ctr_freeze(env, XCTRCTL_LCOFIFRZ, virt);
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} else if (!async && cause == RISCV_EXCP_BREAKPOINT) {
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riscv_ctr_freeze(env, XCTRCTL_BPFRZ, virt);
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}
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riscv_ctr_add_entry(env, src, env->pc,
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async ? CTRDATA_TYPE_INTERRUPT : CTRDATA_TYPE_EXCEPTION,
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prev_priv, prev_virt);
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}
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/*
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