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tcg: Always define TARGET_INSN_START_EXTRA_WORDS

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Do not define TARGET_INSN_START_EXTRA_WORDS under the
hood, have each target explicitly define it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-03-19 12:46:55 +01:00 • committed by Richard Henderson
parent 21d41c566d
commit 4ff1b33edf
10 changed files with 17 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

4
include/tcg/insn-start-words.h
View file

@ -8,10 +8,6 @@
#include "cpu-param.h" #include "cpu-param.h"
#ifndef TARGET_INSN_START_EXTRA_WORDS
# define TARGET_INSN_START_WORDS 1
#else
# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
#endif
#endif /* TARGET_INSN_START_WORDS */ #endif /* TARGET_INSN_START_WORDS */

2
include/tcg/tcg-op.h
View file

@ -23,7 +23,7 @@
# error # error
#endif #endif
#ifndef TARGET_INSN_START_EXTRA_WORDS #if TARGET_INSN_START_EXTRA_WORDS == 0
static inline void tcg_gen_insn_start(target_ulong pc) static inline void tcg_gen_insn_start(target_ulong pc)
{ {
TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS); TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS);

2
target/alpha/cpu-param.h
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@ -24,6 +24,8 @@
# define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
#endif #endif
#define TARGET_INSN_START_EXTRA_WORDS 0
/* Alpha processors have a weak memory model */ /* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0) #define TCG_GUEST_DEFAULT_MO (0)

2
target/avr/cpu-param.h
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@ -25,6 +25,8 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24
#define TARGET_INSN_START_EXTRA_WORDS 0
#define TCG_GUEST_DEFAULT_MO 0 #define TCG_GUEST_DEFAULT_MO 0
#endif #endif

2
target/hexagon/cpu-param.h
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@ -23,4 +23,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_PHYS_ADDR_SPACE_BITS 36
#define TARGET_VIRT_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_INSN_START_EXTRA_WORDS 0
#endif #endif

2
target/loongarch/cpu-param.h
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@ -13,6 +13,8 @@
#define TARGET_PAGE_BITS 12 #define TARGET_PAGE_BITS 12
#define TARGET_INSN_START_EXTRA_WORDS 0
#define TCG_GUEST_DEFAULT_MO (0) #define TCG_GUEST_DEFAULT_MO (0)
#endif #endif

2
target/ppc/cpu-param.h
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@ -37,6 +37,8 @@
# define TARGET_PAGE_BITS 12 # define TARGET_PAGE_BITS 12
#endif #endif
#define TARGET_INSN_START_EXTRA_WORDS 0
#define TCG_GUEST_DEFAULT_MO 0 #define TCG_GUEST_DEFAULT_MO 0
#endif #endif

2
target/rx/cpu-param.h
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@ -24,4 +24,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_INSN_START_EXTRA_WORDS 0
#endif #endif

2
target/tricore/cpu-param.h
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@ -12,4 +12,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_INSN_START_EXTRA_WORDS 0
#endif #endif

2
target/xtensa/cpu-param.h
View file

@ -16,6 +16,8 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif #endif
#define TARGET_INSN_START_EXTRA_WORDS 0
/* Xtensa processors have a weak memory model */ /* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0) #define TCG_GUEST_DEFAULT_MO (0)