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hw/riscv/riscv-iommu: add riscv-iommu-hpm file
The HPM (Hardware Performance Monitor) support consists of almost 7 hundred lines that would be put on top of the base riscv-iommu emulation. To avoid clogging riscv-iommu.c, add a separated riscv-iommu-hpm file that will contain HPM specific code. We'll start by adding riscv_iommu_hpmcycle_read(), a helper that will be called during the riscv_iommu_mmio_read() callback. This change will have no effect on the existing emulation since we're not declaring HPM feature support. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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5 changed files with 110 additions and 2 deletions
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@ -29,6 +29,7 @@
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#include "cpu_bits.h"
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#include "riscv-iommu.h"
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#include "riscv-iommu-bits.h"
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#include "riscv-iommu-hpm.h"
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#include "trace.h"
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#define LIMIT_CACHE_CTX (1U << 7)
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@ -2153,7 +2154,28 @@ static MemTxResult riscv_iommu_mmio_read(void *opaque, hwaddr addr,
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return MEMTX_ACCESS_ERROR;
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}
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ptr = &s->regs_rw[addr];
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/* Compute cycle register value. */
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if ((addr & ~7) == RISCV_IOMMU_REG_IOHPMCYCLES) {
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val = riscv_iommu_hpmcycle_read(s);
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ptr = (uint8_t *)&val + (addr & 7);
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} else if ((addr & ~3) == RISCV_IOMMU_REG_IOCOUNTOVF) {
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/*
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* Software can read RISCV_IOMMU_REG_IOCOUNTOVF before timer
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* callback completes. In which case CY_OF bit in
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* RISCV_IOMMU_IOHPMCYCLES_OVF would be 0. Here we take the
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* CY_OF bit state from RISCV_IOMMU_REG_IOHPMCYCLES register as
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* it's not dependent over the timer callback and is computed
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* from cycle overflow.
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*/
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val = ldq_le_p(&s->regs_rw[addr]);
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val |= (riscv_iommu_hpmcycle_read(s) & RISCV_IOMMU_IOHPMCYCLES_OVF)
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? RISCV_IOMMU_IOCOUNTOVF_CY
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: 0;
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ptr = (uint8_t *)&val + (addr & 3);
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} else {
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ptr = &s->regs_rw[addr];
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}
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val = ldn_le_p(ptr, size);
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*data = val;
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