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target/riscv/cpu.c: remove cpu->cfg.vlen

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There is no need to keep both 'vlen' and 'vlenb'. All existing code
that requires 'vlen' is retrieving it via 'vlenb << 3'.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2024-01-22 13:11:07 -03:00 • committed by Alistair Francis
parent 25669d275c
commit 4f6d036ccc
3 changed files with 6 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

8
target/riscv/cpu.c
View file

@ -1324,7 +1324,6 @@ static void riscv_cpu_init(Object *obj)
/* Default values for non-bool cpu properties */ /* Default values for non-bool cpu properties */
cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, 16); cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, 16);
cpu->cfg.vlen = 128;
cpu->cfg.vlenb = 128 >> 3; cpu->cfg.vlenb = 128 >> 3;
cpu->cfg.elen = 64; cpu->cfg.elen = 64;
cpu->cfg.cbom_blocksize = 64; cpu->cfg.cbom_blocksize = 64;
@ -1816,22 +1815,21 @@ static void prop_vlen_set(Object *obj, Visitor *v, const char *name,
return; return;
} }
if (value != cpu->cfg.vlen && riscv_cpu_is_vendor(obj)) { if (value != cpu->cfg.vlenb && riscv_cpu_is_vendor(obj)) {
cpu_set_prop_err(cpu, name, errp); cpu_set_prop_err(cpu, name, errp);
error_append_hint(errp, "Current '%s' val: %u\n", error_append_hint(errp, "Current '%s' val: %u\n",
name, cpu->cfg.vlen); name, cpu->cfg.vlenb << 3);
return; return;
} }
cpu_option_add_user_setting(name, value); cpu_option_add_user_setting(name, value);
cpu->cfg.vlen = value;
cpu->cfg.vlenb = value >> 3; cpu->cfg.vlenb = value >> 3;
} }
static void prop_vlen_get(Object *obj, Visitor *v, const char *name, static void prop_vlen_get(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp) void *opaque, Error **errp)
{ {
uint16_t value = RISCV_CPU(obj)->cfg.vlen; uint16_t value = RISCV_CPU(obj)->cfg.vlenb << 3;
visit_type_uint16(v, name, &value, errp); visit_type_uint16(v, name, &value, errp);
} }

1
target/riscv/cpu_cfg.h
View file

@ -139,7 +139,6 @@ struct RISCVCPUConfig {
bool ext_XVentanaCondOps; bool ext_XVentanaCondOps;
uint32_t pmu_mask; uint32_t pmu_mask;
uint16_t vlen;
uint16_t vlenb; uint16_t vlenb;
uint16_t elen; uint16_t elen;
uint16_t cbom_blocksize; uint16_t cbom_blocksize;

4
target/riscv/tcg/tcg-cpu.c
View file

@ -298,7 +298,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
Error **errp) Error **errp)
{ {
if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { uint32_t vlen = cfg->vlenb << 3;
if (vlen > RV_VLEN_MAX || vlen < 128) {
error_setg(errp, error_setg(errp,
"Vector extension implementation only supports VLEN " "Vector extension implementation only supports VLEN "
"in the range [128, %d]", RV_VLEN_MAX); "in the range [128, %d]", RV_VLEN_MAX);