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target/arm: Make VMOV scalar <-> gpreg beatwise for MVE

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In a CPU with MVE, the VMOV (vector lane to general-purpose register)
and VMOV (general-purpose register to vector lane) insns are not
predicated, but they are subject to beatwise execution if they
are not in an IT block.

Since our implementation always executes all 4 beats in one tick,
this means only that we need to handle PSR.ECI:
 * we must do the usual check for bad ECI state
 * we must advance ECI state if the insn succeeds
 * if ECI says we should not be executing the beat corresponding
   to the lane of the vector register being accessed then we
   should skip performing the move

Note that if PSR.ECI is non-zero then we cannot be in an IT block.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-45-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-06-17 13:16:28 +01:00
parent 6f060a636b
commit 4f57ef959c
3 changed files with 75 additions and 8 deletions
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4
target/arm/translate-mve.c
View file

@ -57,7 +57,7 @@ static bool mve_check_qreg_bank(DisasContext *s, int qmask)
return qmask < 8;
}
static bool mve_eci_check(DisasContext *s)
bool mve_eci_check(DisasContext *s)
{
/*
* This is a beatwise insn: check that ECI is valid (not a
@ -91,7 +91,7 @@ static void mve_update_eci(DisasContext *s)
}
}
static void mve_update_and_store_eci(DisasContext *s)
void mve_update_and_store_eci(DisasContext *s)
{
/*
* For insns which don't call a helper function that will call