mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 16:23:55 -06:00
target/arm: fix exception syndrome for AArch32 bkpt insn
pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset system/vl.c: Fix handling of '-serial none -serial something' target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array target/arm: Reinstate "vfp" property on AArch32 CPUs doc/sphinx/hxtool.py: add optional label argument to SRST directive hw/arm: Check for CPU types in machine_run_board_init() for various boards pci-host: designware: Limit value range of iATU viewport register hw/arm: Convert some DPRINTF macros to trace events and guest errors hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices hw/arm: Implement BCM2835 SPI Controller -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmW9C84ZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qS6D/wM0/JGEYfaadpuMEOAx4PG AnfScbPqVhx9J31P2Ks3VrB5F108aq/SaL2BmCb3BLF/ECChlhBXIjd7ukdHstts F1TvqtvLGDZQz6wSVUeB0YOvAjGa3vIskn+Xvk9e6Ne6PcXgVnxAof/cPsXUiYNy 6DJjNiLJ/a9Xgq9rjFO6vzW3AL95U6/FmD2F0pOotWXERhNhoyYVV6RtyeqKlDQP yFVk5h601YURk9PeNZn9zpOpZqjAM7PxyF3X50N3Sv+G0uoKSr6b+c3/fDJbJo3+ 0LXomEa8hdheQxm1dLY5OD0JX3bvYxwH41bDg9B0iEdjxUdXt6LfXI9Nvw9BAwix 8AcGJJUaL4XU4uPfHBpRJApM15+MRb0hqfv4ZcGk8e67IIqVeDbKL2clTQGoHSg1 KaB0POhtFx//M/uBOyk/FR2gb2eBNU8GuoCgxdDwh0K5ylcaK1YPiX4Tcglu4iS0 Frvazphb2pO1BK6JiJwN2/9ezzDkDJqTKoSqdc4g3ETVOGnxr+tXwcds3t2iK3g2 y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD jGjDBz6mryWvP2H0xSmERQ== =azdP -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target/arm: fix exception syndrome for AArch32 bkpt insn pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset system/vl.c: Fix handling of '-serial none -serial something' target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array target/arm: Reinstate "vfp" property on AArch32 CPUs doc/sphinx/hxtool.py: add optional label argument to SRST directive hw/arm: Check for CPU types in machine_run_board_init() for various boards pci-host: designware: Limit value range of iATU viewport register hw/arm: Convert some DPRINTF macros to trace events and guest errors hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices hw/arm: Implement BCM2835 SPI Controller # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmW9C84ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qS6D/wM0/JGEYfaadpuMEOAx4PG # AnfScbPqVhx9J31P2Ks3VrB5F108aq/SaL2BmCb3BLF/ECChlhBXIjd7ukdHstts # F1TvqtvLGDZQz6wSVUeB0YOvAjGa3vIskn+Xvk9e6Ne6PcXgVnxAof/cPsXUiYNy # 6DJjNiLJ/a9Xgq9rjFO6vzW3AL95U6/FmD2F0pOotWXERhNhoyYVV6RtyeqKlDQP # yFVk5h601YURk9PeNZn9zpOpZqjAM7PxyF3X50N3Sv+G0uoKSr6b+c3/fDJbJo3+ # 0LXomEa8hdheQxm1dLY5OD0JX3bvYxwH41bDg9B0iEdjxUdXt6LfXI9Nvw9BAwix # 8AcGJJUaL4XU4uPfHBpRJApM15+MRb0hqfv4ZcGk8e67IIqVeDbKL2clTQGoHSg1 # KaB0POhtFx//M/uBOyk/FR2gb2eBNU8GuoCgxdDwh0K5ylcaK1YPiX4Tcglu4iS0 # Frvazphb2pO1BK6JiJwN2/9ezzDkDJqTKoSqdc4g3ETVOGnxr+tXwcds3t2iK3g2 # y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq # yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD # jGjDBz6mryWvP2H0xSmERQ== # =azdP # -----END PGP SIGNATURE----- # gpg: Signature made Fri 02 Feb 2024 15:35:42 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/arm: Connect SPI Controller to BCM2835 hw/ssi: Implement BCM2835 SPI Controller tests/qtest: Adding PCS Module test to GMAC Qtest hw/net: GMAC Tx Implementation hw/net: GMAC Rx Implementation tests/qtest: Creating qtest for GMAC Module hw/arm: Add GMAC devices to NPCM7XX SoC hw/net: Add NPCMXXX GMAC device hw/xen: convert stderr prints to error/warn reports hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports hw/arm/z2: convert DPRINTF to trace events and guest errors hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors pci-host: designware: Limit value range of iATU viewport register hw/arm/zynq: Check for CPU types in machine_run_board_init() hw/arm/vexpress: Check for CPU types in machine_run_board_init() hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
4f2fdb10b5
50 changed files with 2388 additions and 244 deletions
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@ -31,6 +31,7 @@
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#include "hw/gpio/bcm2835_gpio.h"
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#include "hw/timer/bcm2835_systmr.h"
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#include "hw/usb/hcd-dwc2.h"
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#include "hw/ssi/bcm2835_spi.h"
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#include "hw/misc/unimp.h"
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#include "qom/object.h"
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@ -66,7 +67,7 @@ struct BCM2835PeripheralState {
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BCM2835GpioState gpio;
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Bcm2835ThermalState thermal;
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UnimplementedDeviceState i2s;
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UnimplementedDeviceState spi[1];
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BCM2835SPIState spi[1];
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UnimplementedDeviceState i2c[3];
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UnimplementedDeviceState otp;
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UnimplementedDeviceState dbus;
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@ -47,13 +47,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(MSF2State, MSF2_SOC)
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#define MSF2_NUM_TIMERS 2
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struct MSF2State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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ARMv7MState armv7m;
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char *cpu_type;
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char *part_name;
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uint64_t envm_size;
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uint64_t esram_size;
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@ -29,6 +29,7 @@
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#include "hw/misc/npcm7xx_pwm.h"
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#include "hw/misc/npcm7xx_rng.h"
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#include "hw/net/npcm7xx_emc.h"
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#include "hw/net/npcm_gmac.h"
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#include "hw/nvram/npcm7xx_otp.h"
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#include "hw/timer/npcm7xx_timer.h"
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#include "hw/ssi/npcm7xx_fiu.h"
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@ -104,6 +105,7 @@ struct NPCM7xxState {
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OHCISysBusState ohci;
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NPCM7xxFIUState fiu[2];
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NPCM7xxEMCState emc[2];
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NPCMGMACState gmac[2];
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NPCM7xxSDHCIState mmc;
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NPCMPSPIState pspi[2];
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};
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343
include/hw/net/npcm_gmac.h
Normal file
343
include/hw/net/npcm_gmac.h
Normal file
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@ -0,0 +1,343 @@
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/*
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* Nuvoton NPCM7xx/8xx GMAC Module
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*
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* Copyright 2024 Google LLC
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* Authors:
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* Hao Wu <wuhaotsh@google.com>
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* Nabih Estefan <nabihestefan@google.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM_GMAC_H
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#define NPCM_GMAC_H
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "net/net.h"
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#define NPCM_GMAC_NR_REGS (0x1060 / sizeof(uint32_t))
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#define NPCM_GMAC_MAX_PHYS 32
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#define NPCM_GMAC_MAX_PHY_REGS 32
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struct NPCMGMACRxDesc {
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uint32_t rdes0;
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uint32_t rdes1;
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uint32_t rdes2;
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uint32_t rdes3;
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};
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/* NPCMGMACRxDesc.flags values */
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/* RDES2 and RDES3 are buffer addresses */
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/* Owner: 0 = software, 1 = dma */
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#define RX_DESC_RDES0_OWN BIT(31)
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/* Destination Address Filter Fail */
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#define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL BIT(30)
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/* Frame length */
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#define RX_DESC_RDES0_FRAME_LEN_MASK(word) extract32(word, 16, 14)
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/* Frame length Shift*/
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#define RX_DESC_RDES0_FRAME_LEN_SHIFT 16
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/* Error Summary */
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#define RX_DESC_RDES0_ERR_SUMM_MASK BIT(15)
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/* Descriptor Error */
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#define RX_DESC_RDES0_DESC_ERR_MASK BIT(14)
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/* Source Address Filter Fail */
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#define RX_DESC_RDES0_SRC_ADDR_FILT_FAIL_MASK BIT(13)
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/* Length Error */
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#define RX_DESC_RDES0_LEN_ERR_MASK BIT(12)
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/* Overflow Error */
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#define RX_DESC_RDES0_OVRFLW_ERR_MASK BIT(11)
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/* VLAN Tag */
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#define RX_DESC_RDES0_VLAN_TAG_MASK BIT(10)
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/* First Descriptor */
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#define RX_DESC_RDES0_FIRST_DESC_MASK BIT(9)
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/* Last Descriptor */
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#define RX_DESC_RDES0_LAST_DESC_MASK BIT(8)
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/* IPC Checksum Error/Giant Frame */
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#define RX_DESC_RDES0_IPC_CHKSM_ERR_GNT_FRM_MASK BIT(7)
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/* Late Collision */
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#define RX_DESC_RDES0_LT_COLL_MASK BIT(6)
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/* Frame Type */
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#define RX_DESC_RDES0_FRM_TYPE_MASK BIT(5)
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/* Receive Watchdog Timeout */
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#define RX_DESC_RDES0_REC_WTCHDG_TMT_MASK BIT(4)
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/* Receive Error */
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#define RX_DESC_RDES0_RCV_ERR_MASK BIT(3)
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/* Dribble Bit Error */
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#define RX_DESC_RDES0_DRBL_BIT_ERR_MASK BIT(2)
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/* Cyclcic Redundancy Check Error */
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#define RX_DESC_RDES0_CRC_ERR_MASK BIT(1)
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/* Rx MAC Address/Payload Checksum Error */
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#define RC_DESC_RDES0_RCE_MASK BIT(0)
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/* Disable Interrupt on Completion */
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#define RX_DESC_RDES1_DIS_INTR_COMP_MASK BIT(31)
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/* Recieve end of ring */
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#define RX_DESC_RDES1_RC_END_RING_MASK BIT(25)
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/* Second Address Chained */
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#define RX_DESC_RDES1_SEC_ADDR_CHND_MASK BIT(24)
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/* Receive Buffer 2 Size */
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#define RX_DESC_RDES1_BFFR2_SZ_SHIFT 11
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#define RX_DESC_RDES1_BFFR2_SZ_MASK(word) extract32(word, \
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RX_DESC_RDES1_BFFR2_SZ_SHIFT, 11)
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/* Receive Buffer 1 Size */
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#define RX_DESC_RDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 11)
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struct NPCMGMACTxDesc {
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uint32_t tdes0;
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uint32_t tdes1;
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uint32_t tdes2;
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uint32_t tdes3;
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};
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/* NPCMGMACTxDesc.flags values */
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/* TDES2 and TDES3 are buffer addresses */
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/* Owner: 0 = software, 1 = gmac */
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#define TX_DESC_TDES0_OWN BIT(31)
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/* Tx Time Stamp Status */
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#define TX_DESC_TDES0_TTSS_MASK BIT(17)
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/* IP Header Error */
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#define TX_DESC_TDES0_IP_HEAD_ERR_MASK BIT(16)
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/* Error Summary */
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#define TX_DESC_TDES0_ERR_SUMM_MASK BIT(15)
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/* Jabber Timeout */
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#define TX_DESC_TDES0_JBBR_TMT_MASK BIT(14)
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/* Frame Flushed */
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#define TX_DESC_TDES0_FRM_FLSHD_MASK BIT(13)
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/* Payload Checksum Error */
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#define TX_DESC_TDES0_PYLD_CHKSM_ERR_MASK BIT(12)
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/* Loss of Carrier */
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#define TX_DESC_TDES0_LSS_CARR_MASK BIT(11)
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/* No Carrier */
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#define TX_DESC_TDES0_NO_CARR_MASK BIT(10)
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/* Late Collision */
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#define TX_DESC_TDES0_LATE_COLL_MASK BIT(9)
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/* Excessive Collision */
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#define TX_DESC_TDES0_EXCS_COLL_MASK BIT(8)
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/* VLAN Frame */
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#define TX_DESC_TDES0_VLAN_FRM_MASK BIT(7)
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/* Collision Count */
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#define TX_DESC_TDES0_COLL_CNT_MASK(word) extract32(word, 3, 4)
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/* Excessive Deferral */
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#define TX_DESC_TDES0_EXCS_DEF_MASK BIT(2)
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/* Underflow Error */
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#define TX_DESC_TDES0_UNDRFLW_ERR_MASK BIT(1)
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/* Deferred Bit */
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#define TX_DESC_TDES0_DFRD_BIT_MASK BIT(0)
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/* Interrupt of Completion */
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#define TX_DESC_TDES1_INTERR_COMP_MASK BIT(31)
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/* Last Segment */
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#define TX_DESC_TDES1_LAST_SEG_MASK BIT(30)
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/* First Segment */
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#define TX_DESC_TDES1_FIRST_SEG_MASK BIT(29)
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/* Checksum Insertion Control */
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#define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(word) extract32(word, 27, 2)
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/* Disable Cyclic Redundancy Check */
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#define TX_DESC_TDES1_DIS_CDC_MASK BIT(26)
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/* Transmit End of Ring */
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#define TX_DESC_TDES1_TX_END_RING_MASK BIT(25)
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/* Secondary Address Chained */
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#define TX_DESC_TDES1_SEC_ADDR_CHND_MASK BIT(24)
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/* Transmit Buffer 2 Size */
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#define TX_DESC_TDES1_BFFR2_SZ_MASK(word) extract32(word, 11, 11)
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/* Transmit Buffer 1 Size */
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#define TX_DESC_TDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 11)
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typedef struct NPCMGMACState {
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SysBusDevice parent;
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MemoryRegion iomem;
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qemu_irq irq;
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NICState *nic;
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NICConf conf;
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uint32_t regs[NPCM_GMAC_NR_REGS];
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uint16_t phy_regs[NPCM_GMAC_MAX_PHYS][NPCM_GMAC_MAX_PHY_REGS];
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} NPCMGMACState;
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#define TYPE_NPCM_GMAC "npcm-gmac"
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OBJECT_DECLARE_SIMPLE_TYPE(NPCMGMACState, NPCM_GMAC)
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/* Mask for RO bits in Status */
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#define NPCM_DMA_STATUS_RO_MASK(word) (word & 0xfffe0000)
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/* Mask for RO bits in Status */
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#define NPCM_DMA_STATUS_W1C_MASK(word) (word & 0x1e7ff)
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/* Transmit Process State */
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#define NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT 20
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/* Transmit States */
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#define NPCM_DMA_STATUS_TX_STOPPED_STATE \
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(0b000)
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#define NPCM_DMA_STATUS_TX_RUNNING_FETCHING_STATE \
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(0b001)
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#define NPCM_DMA_STATUS_TX_RUNNING_WAITING_STATE \
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(0b010)
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#define NPCM_DMA_STATUS_TX_RUNNING_READ_STATE \
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(0b011)
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#define NPCM_DMA_STATUS_TX_SUSPENDED_STATE \
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(0b110)
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#define NPCM_DMA_STATUS_TX_RUNNING_CLOSING_STATE \
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(0b111)
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/* Transmit Process State */
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#define NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT 17
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/* Receive States */
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#define NPCM_DMA_STATUS_RX_STOPPED_STATE \
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(0b000)
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#define NPCM_DMA_STATUS_RX_RUNNING_FETCHING_STATE \
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(0b001)
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#define NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE \
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(0b011)
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#define NPCM_DMA_STATUS_RX_SUSPENDED_STATE \
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(0b100)
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#define NPCM_DMA_STATUS_RX_RUNNING_CLOSING_STATE \
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(0b101)
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#define NPCM_DMA_STATUS_RX_RUNNING_TRANSFERRING_STATE \
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(0b111)
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/* Early Receive Interrupt */
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#define NPCM_DMA_STATUS_ERI BIT(14)
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/* Fatal Bus Error Interrupt */
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#define NPCM_DMA_STATUS_FBI BIT(13)
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/* Early transmit Interrupt */
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#define NPCM_DMA_STATUS_ETI BIT(10)
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/* Receive Watchdog Timout */
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#define NPCM_DMA_STATUS_RWT BIT(9)
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/* Receive Process Stopped */
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#define NPCM_DMA_STATUS_RPS BIT(8)
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/* Receive Buffer Unavailable */
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#define NPCM_DMA_STATUS_RU BIT(7)
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/* Receive Interrupt */
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#define NPCM_DMA_STATUS_RI BIT(6)
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/* Transmit Underflow */
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#define NPCM_DMA_STATUS_UNF BIT(5)
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/* Receive Overflow */
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#define NPCM_DMA_STATUS_OVF BIT(4)
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/* Transmit Jabber Timeout */
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#define NPCM_DMA_STATUS_TJT BIT(3)
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/* Transmit Buffer Unavailable */
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#define NPCM_DMA_STATUS_TU BIT(2)
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||||
/* Transmit Process Stopped */
|
||||
#define NPCM_DMA_STATUS_TPS BIT(1)
|
||||
/* Transmit Interrupt */
|
||||
#define NPCM_DMA_STATUS_TI BIT(0)
|
||||
|
||||
/* Normal Interrupt Summary */
|
||||
#define NPCM_DMA_STATUS_NIS BIT(16)
|
||||
/* Interrupts enabled by NIE */
|
||||
#define NPCM_DMA_STATUS_NIS_BITS (NPCM_DMA_STATUS_TI | \
|
||||
NPCM_DMA_STATUS_TU | \
|
||||
NPCM_DMA_STATUS_RI | \
|
||||
NPCM_DMA_STATUS_ERI)
|
||||
/* Abnormal Interrupt Summary */
|
||||
#define NPCM_DMA_STATUS_AIS BIT(15)
|
||||
/* Interrupts enabled by AIE */
|
||||
#define NPCM_DMA_STATUS_AIS_BITS (NPCM_DMA_STATUS_TPS | \
|
||||
NPCM_DMA_STATUS_TJT | \
|
||||
NPCM_DMA_STATUS_OVF | \
|
||||
NPCM_DMA_STATUS_UNF | \
|
||||
NPCM_DMA_STATUS_RU | \
|
||||
NPCM_DMA_STATUS_RPS | \
|
||||
NPCM_DMA_STATUS_RWT | \
|
||||
NPCM_DMA_STATUS_ETI | \
|
||||
NPCM_DMA_STATUS_FBI)
|
||||
|
||||
/* Early Receive Interrupt Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_ERE BIT(14)
|
||||
/* Fatal Bus Error Interrupt Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_FBE BIT(13)
|
||||
/* Early transmit Interrupt Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_ETE BIT(10)
|
||||
/* Receive Watchdog Timout Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_RWE BIT(9)
|
||||
/* Receive Process Stopped Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_RSE BIT(8)
|
||||
/* Receive Buffer Unavailable Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_RUE BIT(7)
|
||||
/* Receive Interrupt Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_RIE BIT(6)
|
||||
/* Transmit Underflow Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_UNE BIT(5)
|
||||
/* Receive Overflow Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_OVE BIT(4)
|
||||
/* Transmit Jabber Timeout Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_TJE BIT(3)
|
||||
/* Transmit Buffer Unavailable Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_TUE BIT(2)
|
||||
/* Transmit Process Stopped Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_TSE BIT(1)
|
||||
/* Transmit Interrupt Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_TIE BIT(0)
|
||||
|
||||
/* Normal Interrupt Summary Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_NIE BIT(16)
|
||||
/* Interrupts enabled by NIE Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_NIE_BITS (NPCM_DMA_INTR_ENAB_TIE | \
|
||||
NPCM_DMA_INTR_ENAB_TUE | \
|
||||
NPCM_DMA_INTR_ENAB_RIE | \
|
||||
NPCM_DMA_INTR_ENAB_ERE)
|
||||
/* Abnormal Interrupt Summary Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_AIE BIT(15)
|
||||
/* Interrupts enabled by AIE Enable */
|
||||
#define NPCM_DMA_INTR_ENAB_AIE_BITS (NPCM_DMA_INTR_ENAB_TSE | \
|
||||
NPCM_DMA_INTR_ENAB_TJE | \
|
||||
NPCM_DMA_INTR_ENAB_OVE | \
|
||||
NPCM_DMA_INTR_ENAB_UNE | \
|
||||
NPCM_DMA_INTR_ENAB_RUE | \
|
||||
NPCM_DMA_INTR_ENAB_RSE | \
|
||||
NPCM_DMA_INTR_ENAB_RWE | \
|
||||
NPCM_DMA_INTR_ENAB_ETE | \
|
||||
NPCM_DMA_INTR_ENAB_FBE)
|
||||
|
||||
/* Flushing Disabled */
|
||||
#define NPCM_DMA_CONTROL_FLUSH_MASK BIT(24)
|
||||
/* Start/stop Transmit */
|
||||
#define NPCM_DMA_CONTROL_START_STOP_TX BIT(13)
|
||||
/* Start/stop Receive */
|
||||
#define NPCM_DMA_CONTROL_START_STOP_RX BIT(1)
|
||||
/* Next receive descriptor start address */
|
||||
#define NPCM_DMA_HOST_RX_DESC_MASK(word) ((uint32_t) (word) & ~3u)
|
||||
/* Next transmit descriptor start address */
|
||||
#define NPCM_DMA_HOST_TX_DESC_MASK(word) ((uint32_t) (word) & ~3u)
|
||||
|
||||
/* Receive enable */
|
||||
#define NPCM_GMAC_MAC_CONFIG_RX_EN BIT(2)
|
||||
/* Transmit enable */
|
||||
#define NPCM_GMAC_MAC_CONFIG_TX_EN BIT(3)
|
||||
|
||||
/* Frame Receive All */
|
||||
#define NPCM_GMAC_FRAME_FILTER_REC_ALL_MASK BIT(31)
|
||||
/* Frame HPF Filter*/
|
||||
#define NPCM_GMAC_FRAME_FILTER_HPF_MASK BIT(10)
|
||||
/* Frame SAF Filter*/
|
||||
#define NPCM_GMAC_FRAME_FILTER_SAF_MASK BIT(9)
|
||||
/* Frame SAIF Filter*/
|
||||
#define NPCM_GMAC_FRAME_FILTER_SAIF_MASK BIT(8)
|
||||
/* Frame PCF Filter*/
|
||||
#define NPCM_GMAC_FRAME_FILTER_PCF_MASK BIT(word) extract32((word), 6, 2)
|
||||
/* Frame DBF Filter*/
|
||||
#define NPCM_GMAC_FRAME_FILTER_DBF_MASK BIT(5)
|
||||
/* Frame PM Filter*/
|
||||
#define NPCM_GMAC_FRAME_FILTER_PM_MASK BIT(4)
|
||||
/* Frame DAIF Filter*/
|
||||
#define NPCM_GMAC_FRAME_FILTER_DAIF_MASK BIT(3)
|
||||
/* Frame HMC Filter*/
|
||||
#define NPCM_GMAC_FRAME_FILTER_HMC_MASK BIT(2)
|
||||
/* Frame HUC Filter*/
|
||||
#define NPCM_GMAC_FRAME_FILTER_HUC_MASK BIT(1)
|
||||
/* Frame PR Filter*/
|
||||
#define NPCM_GMAC_FRAME_FILTER_PR_MASK BIT(0)
|
||||
|
||||
#endif /* NPCM_GMAC_H */
|
||||
|
|
@ -329,8 +329,6 @@ struct BusClass {
|
|||
*/
|
||||
char *(*get_fw_dev_path)(DeviceState *dev);
|
||||
|
||||
void (*reset)(BusState *bus);
|
||||
|
||||
/*
|
||||
* Return whether the device can be added to @bus,
|
||||
* based on the address that was set (via device properties)
|
||||
|
|
|
|||
81
include/hw/ssi/bcm2835_spi.h
Normal file
81
include/hw/ssi/bcm2835_spi.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* BCM2835 SPI Master Controller
|
||||
*
|
||||
* Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/ssi/ssi.h"
|
||||
#include "qom/object.h"
|
||||
#include "qemu/fifo8.h"
|
||||
|
||||
#define TYPE_BCM2835_SPI "bcm2835-spi"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(BCM2835SPIState, BCM2835_SPI)
|
||||
|
||||
/*
|
||||
* Though BCM2835 documentation says FIFOs have a capacity of 16,
|
||||
* FIFOs are actually 16 words in size or effectively 64 bytes when operating
|
||||
* in non DMA mode.
|
||||
*/
|
||||
#define FIFO_SIZE 64
|
||||
#define FIFO_SIZE_3_4 48
|
||||
|
||||
#define RO_MASK 0x1f0000
|
||||
|
||||
#define BCM2835_SPI_CS 0x00
|
||||
#define BCM2835_SPI_FIFO 0x04
|
||||
#define BCM2835_SPI_CLK 0x08
|
||||
#define BCM2835_SPI_DLEN 0x0c
|
||||
#define BCM2835_SPI_LTOH 0x10
|
||||
#define BCM2835_SPI_DC 0x14
|
||||
|
||||
#define BCM2835_SPI_CS_RXF BIT(20)
|
||||
#define BCM2835_SPI_CS_RXR BIT(19)
|
||||
#define BCM2835_SPI_CS_TXD BIT(18)
|
||||
#define BCM2835_SPI_CS_RXD BIT(17)
|
||||
#define BCM2835_SPI_CS_DONE BIT(16)
|
||||
#define BCM2835_SPI_CS_LEN BIT(13)
|
||||
#define BCM2835_SPI_CS_REN BIT(12)
|
||||
#define BCM2835_SPI_CS_INTR BIT(10)
|
||||
#define BCM2835_SPI_CS_INTD BIT(9)
|
||||
#define BCM2835_SPI_CS_DMAEN BIT(8)
|
||||
#define BCM2835_SPI_CS_TA BIT(7)
|
||||
#define BCM2835_SPI_CLEAR_RX BIT(5)
|
||||
#define BCM2835_SPI_CLEAR_TX BIT(4)
|
||||
|
||||
struct BCM2835SPIState {
|
||||
/* <private> */
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
/* <public> */
|
||||
SSIBus *bus;
|
||||
MemoryRegion iomem;
|
||||
qemu_irq irq;
|
||||
|
||||
uint32_t cs;
|
||||
uint32_t clk;
|
||||
uint32_t dlen;
|
||||
uint32_t ltoh;
|
||||
uint32_t dc;
|
||||
|
||||
Fifo8 tx_fifo;
|
||||
Fifo8 rx_fifo;
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue