motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-05 00:33:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: redirect XVentanaCondOps to use the Zicond functions

Browse source 
The Zicond standard extension implements the same instruction
semantics as XVentanaCondOps, although using different mnemonics and
opcodes.

Point XVentanaCondOps to the (newly implemented) Zicond implementation
to reduce the future maintenance burden.

Also updating MAINTAINERS as trans_xventanacondops.c.inc.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307180708.302867-3-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philipp Tomsich 2023-03-07 19:07:08 +01:00 • committed by Alistair Francis
parent 378e43fa72
commit 4f2493146d
2 changed files with 4 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

18
target/riscv/insn_trans/trans_xventanacondops.c.inc
View file

@ -1,7 +1,7 @@
/*
* RISC-V translation routines for the XVentanaCondOps extension.
*
* Copyright (c) 2021-2022 VRULL GmbH.
* Copyright (c) 2021-2023 VRULL GmbH.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@ -16,24 +16,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
{
TCGv dest = dest_gpr(ctx, a->rd);
TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
{
return gen_vt_condmask(ctx, a, TCG_COND_NE);
return gen_logic(ctx, a, gen_czero_eqz);
}
static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
{
return gen_vt_condmask(ctx, a, TCG_COND_EQ);
return gen_logic(ctx, a, gen_czero_nez);
}