mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-06 17:23:56 -06:00
tcg: implement real ext_i32_i64 and extu_i32_i64 ops
Implement real ext_i32_i64 and extu_i32_i64 ops. They ensure that a 32-bit value is always converted to a 64-bit value and not propagated through the register allocator or the optimizer. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Stefan Weil <sw@weilnetz.de> Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
parent
6acd2558fd
commit
4f2331e5b6
10 changed files with 45 additions and 10 deletions
|
@ -210,6 +210,8 @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
|
|||
#if TCG_TARGET_HAS_ext32u_i64
|
||||
{ INDEX_op_ext32u_i64, { R, R } },
|
||||
#endif
|
||||
{ INDEX_op_ext_i32_i64, { R, R } },
|
||||
{ INDEX_op_extu_i32_i64, { R, R } },
|
||||
#if TCG_TARGET_HAS_bswap16_i64
|
||||
{ INDEX_op_bswap16_i64, { R, R } },
|
||||
#endif
|
||||
|
@ -701,6 +703,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
|
|||
case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */
|
||||
case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */
|
||||
case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */
|
||||
case INDEX_op_ext_i32_i64:
|
||||
case INDEX_op_extu_i32_i64:
|
||||
#endif /* TCG_TARGET_REG_BITS == 64 */
|
||||
case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */
|
||||
case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue