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target/riscv: add RVG and remove cpu->cfg.ext_g

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We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it
the same way we did with the others: create a "g" RISCVCPUMisaExtConfig
property, remove the old "g" property, remove all instances of 'cfg.ext_g'
and use riscv_has_ext(env, RVG).

The caveat is that we don't have RVG, so add it. RVG will be used right
off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is
enabling G via the now removed 'ext_g' flag.

After this patch, there are no more MISA extensions represented by flags
in RISCVCPUConfig.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-20-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:50 -03:00 • committed by Alistair Francis
parent 8ef67c6637
commit 4f13abcb2b
2 changed files with 9 additions and 10 deletions
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2
target/riscv/cpu.h
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@ -81,6 +81,7 @@
#define RVU RV('U')
#define RVH RV('H')
#define RVJ RV('J')
#define RVG RV('G')
/* Privileged specification version */
@ -422,7 +423,6 @@ typedef struct {
} RISCVSATPMap;
struct RISCVCPUConfig {
bool ext_g;
bool ext_zba;
bool ext_zbb;
bool ext_zbc;