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linux-user/sparc: Handle floating-point exceptions

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Raise SIGFPE for ieee exceptions.

The other types, such as FSR_FTT_UNIMPFPOP, should not appear,
because we enable normal emulation of missing insns at the
start of sparc_cpu_realizefn().

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230216054516.1267305-15-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
This commit is contained in:
Richard Henderson 2023-02-15 19:45:15 -10:00 • committed by Laurent Vivier
parent 81f04cd34c
commit 4ea3af392f
2 changed files with 23 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

22
linux-user/sparc/cpu_loop.c
View file

@ -297,6 +297,28 @@ void cpu_loop (CPUSPARCState *env)
restore_window(env); restore_window(env);
break; break;
case TT_FP_EXCP:
{
int code = TARGET_FPE_FLTUNK;
target_ulong fsr = env->fsr;
if ((fsr & FSR_FTT_MASK) == FSR_FTT_IEEE_EXCP) {
if (fsr & FSR_NVC) {
code = TARGET_FPE_FLTINV;
} else if (fsr & FSR_OFC) {
code = TARGET_FPE_FLTOVF;
} else if (fsr & FSR_UFC) {
code = TARGET_FPE_FLTUND;
} else if (fsr & FSR_DZC) {
code = TARGET_FPE_FLTDIV;
} else if (fsr & FSR_NXC) {
code = TARGET_FPE_FLTRES;
}
}
force_sig_fault(TARGET_SIGFPE, code, env->pc);
}
break;
case EXCP_INTERRUPT: case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */ /* just indicate that signals should be handled asap */
break; break;

3
target/sparc/cpu.h
View file

@ -197,8 +197,7 @@ enum {
#define FSR_FTT2 (1ULL << 16) #define FSR_FTT2 (1ULL << 16)
#define FSR_FTT1 (1ULL << 15) #define FSR_FTT1 (1ULL << 15)
#define FSR_FTT0 (1ULL << 14) #define FSR_FTT0 (1ULL << 14)
//gcc warns about constant overflow for ~FSR_FTT_MASK #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
#define FSR_FTT_NMASK 0xfffffffffffe3fffULL #define FSR_FTT_NMASK 0xfffffffffffe3fffULL
#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL