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Fix [ls][wd][lr] instructions, by Aurelien Jarno.

Browse source 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3372 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-10-09 03:12:08 +00:00
parent 0e21e12bb3
commit 4e9f853731
5 changed files with 207 additions and 68 deletions
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8
target-mips/translate.c
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@ -889,7 +889,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
case OPC_LDL:
GEN_LOAD_REG_TN(T1, rt);
op_ldst(ldl);
GEN_STORE_TN_REG(rt, T0);
GEN_STORE_TN_REG(rt, T1);
opn = "ldl";
break;
case OPC_SDL:
@ -900,7 +900,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
case OPC_LDR:
GEN_LOAD_REG_TN(T1, rt);
op_ldst(ldr);
GEN_STORE_TN_REG(rt, T0);
GEN_STORE_TN_REG(rt, T1);
opn = "ldr";
break;
case OPC_SDR:
@ -952,7 +952,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
case OPC_LWL:
GEN_LOAD_REG_TN(T1, rt);
op_ldst(lwl);
GEN_STORE_TN_REG(rt, T0);
GEN_STORE_TN_REG(rt, T1);
opn = "lwl";
break;
case OPC_SWL:
@ -963,7 +963,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
case OPC_LWR:
GEN_LOAD_REG_TN(T1, rt);
op_ldst(lwr);
GEN_STORE_TN_REG(rt, T0);
GEN_STORE_TN_REG(rt, T1);
opn = "lwr";
break;
case OPC_SWR: