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Reworking MIPS interrupt handling, by Aurelien Jarno.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-01-24 01:47:51 +00:00
parent 30c4bbace1
commit 4de9b249d3
13 changed files with 76 additions and 75 deletions
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9
hw/mips_r4k.c
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@ -38,14 +38,7 @@ static PITState *pit; /* PIT i8254 */
/*The PIC is attached to the MIPS CPU INT0 pin */
static void pic_irq_request(void *opaque, int level)
{
CPUState *env = first_cpu;
if (level) {
env->CP0_Cause |= 0x00000400;
cpu_interrupt(env, CPU_INTERRUPT_HARD);
} else {
env->CP0_Cause &= ~0x00000400;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
cpu_mips_irq_request(opaque, 2, level);
}
static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,