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Reworking MIPS interrupt handling, by Aurelien Jarno.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-01-24 01:47:51 +00:00
parent 30c4bbace1
commit 4de9b249d3
13 changed files with 76 additions and 75 deletions
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39
hw/mips_int.c Normal file
View file

@ -0,0 +1,39 @@
#include "vl.h"
#include "cpu.h"
/* Raise IRQ to CPU if necessary. It must be called every time the active
IRQ may change */
void cpu_mips_update_irq(CPUState *env)
{
if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
(env->CP0_Status & (1 << CP0St_IE)) &&
!(env->hflags & MIPS_HFLAG_EXL) &&
!(env->hflags & MIPS_HFLAG_ERL) &&
!(env->hflags & MIPS_HFLAG_DM)) {
if (! (env->interrupt_request & CPU_INTERRUPT_HARD)) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
} else {
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
}
void cpu_mips_irq_request(void *opaque, int irq, int level)
{
CPUState *env = first_cpu;
uint32_t mask;
if (irq >= 16)
return;
mask = 1 << (irq + CP0Ca_IP);
if (level) {
env->CP0_Cause |= mask;
} else {
env->CP0_Cause &= ~mask;
}
cpu_mips_update_irq(env);
}