motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 08:13:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

Sparc32: dummy implementation of MXCC MMU breakpoint registers

Browse source 
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, save
and load all MXCC registers.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2011-06-18 20:27:05 +00:00
parent af2be20777
commit 4d2c2b77f3
3 changed files with 53 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

26
target-sparc/op_helper.c
View file

@ -1940,7 +1940,6 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
case 0x31: // Turbosparc RAM snoop
case 0x32: // Turbosparc page table descriptor diagnostic
case 0x39: /* data cache diagnostic register */
case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
ret = 0;
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
@ -1966,6 +1965,18 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
ret);
}
break;
case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
ret = env->mmubpctrv;
break;
case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
ret = env->mmubpctrc;
break;
case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
ret = env->mmubpctrs;
break;
case 0x4c: /* SuperSPARC MMU Breakpoint Action */
ret = env->mmubpaction;
break;
case 8: /* User code access, XXX */
default:
do_unassigned_access(addr, 0, 0, asi, size);
@ -2304,7 +2315,6 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
// descriptor diagnostic
case 0x36: /* I-cache flash clear */
case 0x37: /* D-cache flash clear */
case 0x4c: /* breakpoint action */
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
{
@ -2328,6 +2338,18 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
env->mmuregs[reg]);
}
break;
case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
env->mmubpctrv = val & 0xffffffff;
break;
case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
env->mmubpctrc = val & 0x3;
break;
case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
env->mmubpctrs = val & 0x3;
break;
case 0x4c: /* SuperSPARC MMU Breakpoint Action */
env->mmubpaction = val & 0x1fff;
break;
case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
default: