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qemu-sparc update

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-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQEcBAABAgAGBQJU/vQnAAoJEFvCxW+uDzIfSHQIAKLVePJyOEtVA5OOUSyuA5TQ
 6MNXg1X+PxD0GT8iyKhcyHqaRSibPjY/D2Hb8MyNt/lLIQj13hfL1fXXAMvnjY1+
 WcCpGfbZmmcIpgjY+OWkkSVU3nSxNE6a0ZgdOvK9Cvc+dJHMpO02E5kRqig6nYX6
 UuA7aIgjE2T63PPucuEjFVA4a8v7NsqO4OBmYPO/L7KEpAQk3Y/qDDGahQRXuBXl
 0poyJrj99BoKHJFemf7L79SbpZHrnaQ54dndqerq5tzmBXRVjhYJa/iLm0LSjPnN
 kWdlMKXSGgI/rFRWZqfOk+jDIZb21xliM6y/lDpDJGdoC1aPsIWwQ0mFK6ZPVDo=
 =Ee+Y
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging

qemu-sparc update

# gpg: Signature made Tue Mar 10 13:39:51 2015 GMT using RSA key ID AE0F321F
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>"

* remotes/mcayland/tags/qemu-sparc-signed:
  sun4u: switch m48t59 NVRAM to MMIO access
  MAINTAINERS: add myself as SPARC maintainer
  doc: minor updates to SPARC32 and SPARC64 documentation
  m48t59: add m48t59 sysbus device
  m48t59: introduce new base-year qdev property
  m48t59: let init functions return a Nvram object
  m48t59: add a Nvram interface
  m48t59: register a QOM type for each nvram type we support
  m48t59: move ISA ports/memory regions registration to QOM constructor

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2015-03-11 08:44:59 +00:00
commit 4ba4df405c
13 changed files with 463 additions and 323 deletions
Download patch file Download diff file Expand all files Collapse all files

367
hw/timer/m48t59.c
View file

@ -2,6 +2,7 @@
* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
*
* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
* Copyright (c) 2013 Hervé Poussineau
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -37,12 +38,35 @@
#define NVRAM_PRINTF(fmt, ...) do { } while (0)
#endif
#define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
#define M48TXX_SYS_BUS_GET_CLASS(obj) \
OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
#define M48TXX_SYS_BUS_CLASS(klass) \
OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
#define M48TXX_SYS_BUS(obj) \
OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
#define TYPE_M48TXX_ISA "isa-m48txx"
#define M48TXX_ISA_GET_CLASS(obj) \
OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
#define M48TXX_ISA_CLASS(klass) \
OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
#define M48TXX_ISA(obj) \
OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
/*
* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
* alarm and a watchdog timer and related control registers. In the
* PPC platform there is also a nvram lock function.
*/
typedef struct M48txxInfo {
const char *isa_name;
const char *sysbus_name;
uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
uint32_t size;
} M48txxInfo;
/*
* Chipset docs:
* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
@ -50,12 +74,12 @@
* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
*/
struct M48t59State {
typedef struct M48t59State {
/* Hardware parameters */
qemu_irq IRQ;
MemoryRegion iomem;
uint32_t io_base;
uint32_t size;
int32_t base_year;
/* RTC management */
time_t time_offset;
time_t stop_time;
@ -70,28 +94,51 @@ struct M48t59State {
/* NVRAM storage */
uint16_t addr;
uint8_t lock;
} M48t59State;
typedef struct M48txxISAState {
ISADevice parent_obj;
M48t59State state;
uint32_t io_base;
MemoryRegion io;
} M48txxISAState;
typedef struct M48txxISADeviceClass {
ISADeviceClass parent_class;
M48txxInfo info;
} M48txxISADeviceClass;
typedef struct M48txxSysBusState {
SysBusDevice parent_obj;
M48t59State state;
MemoryRegion io;
} M48txxSysBusState;
typedef struct M48txxSysBusDeviceClass {
SysBusDeviceClass parent_class;
M48txxInfo info;
} M48txxSysBusDeviceClass;
static M48txxInfo m48txx_info[] = {
{
.sysbus_name = "sysbus-m48t02",
.model = 2,
.size = 0x800,
},{
.sysbus_name = "sysbus-m48t08",
.model = 8,
.size = 0x2000,
},{
.sysbus_name = "sysbus-m48t59",
.model = 59,
.size = 0x2000,
},{
.isa_name = "isa-m48t59",
.model = 59,
.size = 0x2000,
}
};
#define TYPE_ISA_M48T59 "m48t59_isa"
#define ISA_M48T59(obj) \
OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59)
typedef struct M48t59ISAState {
ISADevice parent_obj;
M48t59State state;
MemoryRegion io;
} M48t59ISAState;
#define SYSBUS_M48T59(obj) \
OBJECT_CHECK(M48t59SysBusState, (obj), TYPE_SYSBUS_M48T59)
typedef struct M48t59SysBusState {
SysBusDevice parent_obj;
M48t59State state;
MemoryRegion io;
} M48t59SysBusState;
/* Fake timer functions */
@ -198,9 +245,8 @@ static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
}
/* Direct access to NVRAM */
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
static void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
{
M48t59State *NVRAM = opaque;
struct tm tm;
int tmp;
@ -346,11 +392,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
tmp = from_bcd(val);
if (tmp >= 0 && tmp <= 99) {
get_time(NVRAM, &tm);
if (NVRAM->model == 8) {
tm.tm_year = from_bcd(val) + 68; // Base year is 1968
} else {
tm.tm_year = from_bcd(val);
}
tm.tm_year = from_bcd(val) + NVRAM->base_year - 1900;
set_time(NVRAM, &tm);
}
break;
@ -368,9 +410,8 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
}
}
uint32_t m48t59_read (void *opaque, uint32_t addr)
static uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
{
M48t59State *NVRAM = opaque;
struct tm tm;
uint32_t retval = 0xFF;
@ -453,11 +494,7 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
case 0x07FF:
/* year */
get_time(NVRAM, &tm);
if (NVRAM->model == 8) {
retval = to_bcd(tm.tm_year - 68); // Base year is 1968
} else {
retval = to_bcd(tm.tm_year);
}
retval = to_bcd((tm.tm_year + 1900 - NVRAM->base_year) % 100);
break;
default:
/* Check lock registers state */
@ -477,10 +514,8 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
return retval;
}
void m48t59_toggle_lock (void *opaque, int lock)
static void m48t59_toggle_lock(M48t59State *NVRAM, int lock)
{
M48t59State *NVRAM = opaque;
NVRAM->lock ^= 1 << lock;
}
@ -616,7 +651,7 @@ static void m48t59_reset_common(M48t59State *NVRAM)
static void m48t59_reset_isa(DeviceState *d)
{
M48t59ISAState *isa = ISA_M48T59(d);
M48txxISAState *isa = M48TXX_ISA(d);
M48t59State *NVRAM = &isa->state;
m48t59_reset_common(NVRAM);
@ -624,7 +659,7 @@ static void m48t59_reset_isa(DeviceState *d)
static void m48t59_reset_sysbus(DeviceState *d)
{
M48t59SysBusState *sys = SYSBUS_M48T59(d);
M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
M48t59State *NVRAM = &sys->state;
m48t59_reset_common(NVRAM);
@ -641,58 +676,63 @@ static const MemoryRegionOps m48t59_io_ops = {
};
/* Initialisation routine */
M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
uint32_t io_base, uint16_t size, int model)
Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
uint32_t io_base, uint16_t size, int base_year,
int model)
{
DeviceState *dev;
SysBusDevice *s;
M48t59SysBusState *d;
M48t59State *state;
int i;
dev = qdev_create(NULL, TYPE_SYSBUS_M48T59);
qdev_prop_set_uint32(dev, "model", model);
qdev_prop_set_uint32(dev, "size", size);
qdev_prop_set_uint32(dev, "io_base", io_base);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
d = SYSBUS_M48T59(dev);
state = &d->state;
sysbus_connect_irq(s, 0, IRQ);
memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, state,
"m48t59", 4);
if (io_base != 0) {
memory_region_add_subregion(get_system_io(), io_base, &d->io);
}
if (mem_base != 0) {
sysbus_mmio_map(s, 0, mem_base);
for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
if (!m48txx_info[i].sysbus_name ||
m48txx_info[i].size != size ||
m48txx_info[i].model != model) {
continue;
}
dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
qdev_prop_set_int32(dev, "base-year", base_year);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(s, 0, IRQ);
if (io_base != 0) {
memory_region_add_subregion(get_system_io(), io_base,
sysbus_mmio_get_region(s, 1));
}
if (mem_base != 0) {
sysbus_mmio_map(s, 0, mem_base);
}
return NVRAM(s);
}
return state;
assert(false);
return NULL;
}
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
int model)
Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
int base_year, int model)
{
M48t59ISAState *d;
ISADevice *isadev;
DeviceState *dev;
M48t59State *s;
int i;
isadev = isa_create(bus, TYPE_ISA_M48T59);
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "model", model);
qdev_prop_set_uint32(dev, "size", size);
qdev_prop_set_uint32(dev, "io_base", io_base);
qdev_init_nofail(dev);
d = ISA_M48T59(isadev);
s = &d->state;
for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
if (!m48txx_info[i].isa_name ||
m48txx_info[i].size != size ||
m48txx_info[i].model != model) {
continue;
}
memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, s, "m48t59", 4);
if (io_base != 0) {
isa_register_ioport(isadev, &d->io, io_base);
dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name));
qdev_prop_set_uint32(dev, "iobase", io_base);
qdev_prop_set_int32(dev, "base-year", base_year);
qdev_init_nofail(dev);
return NVRAM(dev);
}
return s;
assert(false);
return NULL;
}
static void m48t59_realize_common(M48t59State *s, Error **errp)
@ -709,25 +749,38 @@ static void m48t59_realize_common(M48t59State *s, Error **errp)
static void m48t59_isa_realize(DeviceState *dev, Error **errp)
{
M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
ISADevice *isadev = ISA_DEVICE(dev);
M48t59ISAState *d = ISA_M48T59(dev);
M48txxISAState *d = M48TXX_ISA(dev);
M48t59State *s = &d->state;
s->model = u->info.model;
s->size = u->info.size;
isa_init_irq(isadev, &s->IRQ, 8);
m48t59_realize_common(s, errp);
memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
if (d->io_base != 0) {
isa_register_ioport(isadev, &d->io, d->io_base);
}
}
static int m48t59_init1(SysBusDevice *dev)
{
M48t59SysBusState *d = SYSBUS_M48T59(dev);
M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(dev);
M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
Object *o = OBJECT(dev);
M48t59State *s = &d->state;
Error *err = NULL;
s->model = u->info.model;
s->size = u->info.size;
sysbus_init_irq(dev, &s->IRQ);
memory_region_init_io(&s->iomem, OBJECT(d), &nvram_ops, s,
"m48t59.nvram", s->size);
memory_region_init_io(&s->iomem, o, &nvram_ops, s, "m48t59.nvram",
s->size);
memory_region_init_io(&d->io, o, &m48t59_io_ops, s, "m48t59", 4);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(dev, &d->io);
m48t59_realize_common(s, &err);
if (err != NULL) {
error_free(err);
@ -737,59 +790,157 @@ static int m48t59_init1(SysBusDevice *dev)
return 0;
}
static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
{
M48txxISAState *d = M48TXX_ISA(obj);
return m48t59_read(&d->state, addr);
}
static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
{
M48txxISAState *d = M48TXX_ISA(obj);
m48t59_write(&d->state, addr, val);
}
static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
{
M48txxISAState *d = M48TXX_ISA(obj);
m48t59_toggle_lock(&d->state, lock);
}
static Property m48t59_isa_properties[] = {
DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1),
DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1),
DEFINE_PROP_UINT32("io_base", M48t59ISAState, state.io_base, 0),
DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
DEFINE_PROP_END_OF_LIST(),
};
static void m48t59_isa_class_init(ObjectClass *klass, void *data)
static void m48txx_isa_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
NvramClass *nc = NVRAM_CLASS(klass);
dc->realize = m48t59_isa_realize;
dc->reset = m48t59_reset_isa;
dc->props = m48t59_isa_properties;
/* Reason: needs to be wired up by m48t59_init_isa() */
dc->cannot_instantiate_with_device_add_yet = true;
nc->read = m48txx_isa_read;
nc->write = m48txx_isa_write;
nc->toggle_lock = m48txx_isa_toggle_lock;
}
static const TypeInfo m48t59_isa_info = {
.name = TYPE_ISA_M48T59,
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(M48t59ISAState),
.class_init = m48t59_isa_class_init,
};
static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
{
M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
M48txxInfo *info = data;
static Property m48t59_properties[] = {
DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1),
DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1),
DEFINE_PROP_UINT32("io_base", M48t59SysBusState, state.io_base, 0),
u->info = *info;
}
static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
{
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
return m48t59_read(&d->state, addr);
}
static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val)
{
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
m48t59_write(&d->state, addr, val);
}
static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock)
{
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
m48t59_toggle_lock(&d->state, lock);
}
static Property m48t59_sysbus_properties[] = {
DEFINE_PROP_INT32("base-year", M48txxSysBusState, state.base_year, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void m48t59_class_init(ObjectClass *klass, void *data)
static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
NvramClass *nc = NVRAM_CLASS(klass);
k->init = m48t59_init1;
dc->reset = m48t59_reset_sysbus;
dc->props = m48t59_properties;
dc->props = m48t59_sysbus_properties;
nc->read = m48txx_sysbus_read;
nc->write = m48txx_sysbus_write;
nc->toggle_lock = m48txx_sysbus_toggle_lock;
}
static const TypeInfo m48t59_info = {
.name = TYPE_SYSBUS_M48T59,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(M48t59SysBusState),
.class_init = m48t59_class_init,
static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
{
M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
M48txxInfo *info = data;
u->info = *info;
}
static const TypeInfo nvram_info = {
.name = TYPE_NVRAM,
.parent = TYPE_INTERFACE,
.class_size = sizeof(NvramClass),
};
static const TypeInfo m48txx_sysbus_type_info = {
.name = TYPE_M48TXX_SYS_BUS,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(M48txxSysBusState),
.abstract = true,
.class_init = m48txx_sysbus_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_NVRAM },
{ }
}
};
static const TypeInfo m48txx_isa_type_info = {
.name = TYPE_M48TXX_ISA,
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(M48txxISAState),
.abstract = true,
.class_init = m48txx_isa_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_NVRAM },
{ }
}
};
static void m48t59_register_types(void)
{
type_register_static(&m48t59_info);
type_register_static(&m48t59_isa_info);
TypeInfo sysbus_type_info = {
.parent = TYPE_M48TXX_SYS_BUS,
.class_size = sizeof(M48txxSysBusDeviceClass),
.class_init = m48txx_sysbus_concrete_class_init,
};
TypeInfo isa_type_info = {
.parent = TYPE_M48TXX_ISA,
.class_size = sizeof(M48txxISADeviceClass),
.class_init = m48txx_isa_concrete_class_init,
};
int i;
type_register_static(&nvram_info);
type_register_static(&m48txx_sysbus_type_info);
type_register_static(&m48txx_isa_type_info);
for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
if (m48txx_info[i].sysbus_name) {
sysbus_type_info.name = m48txx_info[i].sysbus_name;
sysbus_type_info.class_data = &m48txx_info[i];
type_register(&sysbus_type_info);
}
if (m48txx_info[i].isa_name) {
isa_type_info.name = m48txx_info[i].isa_name;
isa_type_info.class_data = &m48txx_info[i];
type_register(&isa_type_info);
}
}
}
type_init(m48t59_register_types)