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intel-iommu: optimize nodmar memory regions
Previously we have per-device system memory aliases when DMAR is disabled by the system. It will slow the system down if there are lots of devices especially when DMAR is disabled, because each of the aliased system address space will contain O(N) slots, and rendering such N address spaces will be O(N^2) complexity. This patch introduces a shared nodmar memory region and for each device we only create an alias to the shared memory region. With the aliasing, QEMU memory core API will be able to detect when devices are sharing the same address space (which is the nodmar address space) when rendering the FlatViews and the total number of FlatViews can be dramatically reduced when there are a lot of devices. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20190313094323.18263-1-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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2 changed files with 64 additions and 36 deletions
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@ -105,8 +105,8 @@ struct VTDAddressSpace {
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uint8_t devfn;
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AddressSpace as;
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IOMMUMemoryRegion iommu;
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MemoryRegion root;
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MemoryRegion sys_alias;
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MemoryRegion root; /* The root container of the device */
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MemoryRegion nodmar; /* The alias of shared nodmar MR */
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MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */
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IntelIOMMUState *iommu_state;
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VTDContextCacheEntry context_cache_entry;
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@ -221,6 +221,9 @@ union VTD_IR_MSIAddress {
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struct IntelIOMMUState {
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X86IOMMUState x86_iommu;
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MemoryRegion csrmem;
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MemoryRegion mr_nodmar;
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MemoryRegion mr_ir;
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MemoryRegion mr_sys_alias;
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uint8_t csr[DMAR_REG_SIZE]; /* register values */
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uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */
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uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
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