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https://github.com/Motorhead1991/qemu.git
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Sparc32: move device instantiation to sun4m.c
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
7204ff9c79
commit
4b48bf059b
10 changed files with 217 additions and 245 deletions
217
hw/sun4m.c
217
hw/sun4m.c
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@ -36,6 +36,7 @@
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#include "isa.h"
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#include "fw_cfg.h"
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#include "escc.h"
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#include "qdev-addr.h"
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//#define DEBUG_IRQ
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@ -364,6 +365,21 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename,
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return kernel_size;
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}
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static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, "iommu");
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qdev_prop_set_uint32(dev, "version", version);
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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sysbus_connect_irq(s, 0, irq);
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sysbus_mmio_map(s, 0, addr);
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return s;
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}
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static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
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void *dma_opaque, qemu_irq irq, qemu_irq *reset)
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{
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@ -382,6 +398,167 @@ static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
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*reset = qdev_get_gpio_in(dev, 0);
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}
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static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
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target_phys_addr_t addrg,
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const uint32_t *intbit_to_level,
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qemu_irq **parent_irq,
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unsigned int cputimer)
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{
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DeviceState *dev;
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SysBusDevice *s;
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unsigned int i, j;
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dev = qdev_create(NULL, "slavio_intctl");
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qdev_prop_set_ptr(dev, "intbit_to_level", (void *)intbit_to_level);
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qdev_prop_set_uint32(dev, "cputimer_bit", cputimer);
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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for (i = 0; i < MAX_CPUS; i++) {
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for (j = 0; j < MAX_PILS; j++) {
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sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
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}
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}
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sysbus_mmio_map(s, 0, addrg);
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for (i = 0; i < MAX_CPUS; i++) {
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sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
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}
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return dev;
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}
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#define SYS_TIMER_OFFSET 0x10000ULL
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#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
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static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
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qemu_irq *cpu_irqs, unsigned int num_cpus)
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{
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DeviceState *dev;
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SysBusDevice *s;
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unsigned int i;
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dev = qdev_create(NULL, "slavio_timer");
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qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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sysbus_connect_irq(s, 0, master_irq);
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sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
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for (i = 0; i < MAX_CPUS; i++) {
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sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
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sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
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}
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}
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#define MISC_LEDS 0x01600000
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#define MISC_CFG 0x01800000
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#define MISC_DIAG 0x01a00000
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#define MISC_MDM 0x01b00000
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#define MISC_SYS 0x01f00000
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static void *slavio_misc_init(target_phys_addr_t base,
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target_phys_addr_t aux1_base,
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target_phys_addr_t aux2_base, qemu_irq irq,
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qemu_irq fdc_tc)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, "slavio_misc");
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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if (base) {
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/* 8 bit registers */
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/* Slavio control */
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sysbus_mmio_map(s, 0, base + MISC_CFG);
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/* Diagnostics */
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sysbus_mmio_map(s, 1, base + MISC_DIAG);
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/* Modem control */
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sysbus_mmio_map(s, 2, base + MISC_MDM);
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/* 16 bit registers */
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/* ss600mp diag LEDs */
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sysbus_mmio_map(s, 3, base + MISC_LEDS);
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/* 32 bit registers */
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/* System control */
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sysbus_mmio_map(s, 4, base + MISC_SYS);
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}
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if (aux1_base) {
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/* AUX 1 (Misc System Functions) */
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sysbus_mmio_map(s, 5, aux1_base);
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}
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if (aux2_base) {
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/* AUX 2 (Software Powerdown Control) */
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sysbus_mmio_map(s, 6, aux2_base);
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}
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sysbus_connect_irq(s, 0, irq);
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sysbus_connect_irq(s, 1, fdc_tc);
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return s;
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}
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static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, "eccmemctl");
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qdev_prop_set_uint32(dev, "version", version);
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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sysbus_connect_irq(s, 0, irq);
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sysbus_mmio_map(s, 0, base);
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if (version == 0) { // SS-600MP only
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sysbus_mmio_map(s, 1, base + 0x1000);
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}
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}
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static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, "apc");
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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/* Power management (APC) XXX: not a Slavio device */
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sysbus_mmio_map(s, 0, power_base);
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sysbus_connect_irq(s, 0, cpu_halt);
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}
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static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
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int height, int depth)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, "SUNW,tcx");
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qdev_prop_set_taddr(dev, "addr", addr);
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qdev_prop_set_uint32(dev, "vram_size", vram_size);
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qdev_prop_set_uint16(dev, "width", width);
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qdev_prop_set_uint16(dev, "height", height);
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qdev_prop_set_uint16(dev, "depth", depth);
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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/* 8-bit plane */
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sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
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/* DAC */
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sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
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/* TEC (dummy) */
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sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
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/* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
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sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
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if (depth == 24) {
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/* 24-bit plane */
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sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
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/* Control plane */
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sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
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} else {
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/* THC 8 bit (dummy) */
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sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
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}
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}
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/* NCR89C100/MACIO Internal ID register */
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static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
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@ -1314,6 +1491,26 @@ static const struct sun4d_hwdef sun4d_hwdefs[] = {
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},
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};
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static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
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{
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DeviceState *dev;
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SysBusDevice *s;
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unsigned int i;
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dev = qdev_create(NULL, "sbi");
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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for (i = 0; i < MAX_CPUS; i++) {
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sysbus_connect_irq(s, i, *parent_irq[i]);
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}
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sysbus_mmio_map(s, 0, addr);
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return dev;
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}
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static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
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const char *boot_device,
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const char *kernel_filename,
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@ -1494,6 +1691,26 @@ static const struct sun4c_hwdef sun4c_hwdefs[] = {
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},
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};
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static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
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qemu_irq *parent_irq)
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{
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DeviceState *dev;
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SysBusDevice *s;
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unsigned int i;
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dev = qdev_create(NULL, "sun4c_intctl");
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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for (i = 0; i < MAX_PILS; i++) {
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sysbus_connect_irq(s, i, parent_irq[i]);
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}
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sysbus_mmio_map(s, 0, addr);
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return dev;
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}
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static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
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const char *boot_device,
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const char *kernel_filename,
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