mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-05 16:53:55 -06:00
MIPS fixes (Daniel Jacobowitz)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1690 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
6810e15490
commit
4ad40f366f
8 changed files with 232 additions and 105 deletions
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@ -338,17 +338,25 @@ static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
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}
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}
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static inline void generate_exception (DisasContext *ctx, int excp)
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static inline void generate_exception_err (DisasContext *ctx, int excp, int err)
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{
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#if defined MIPS_DEBUG_DISAS
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile, "%s: raise exception %d\n", __func__, excp);
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#endif
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save_cpu_state(ctx, 1);
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gen_op_raise_exception(excp);
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if (err == 0)
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gen_op_raise_exception(excp);
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else
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gen_op_raise_exception_err(excp, err);
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ctx->bstate = BS_EXCP;
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}
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static inline void generate_exception (DisasContext *ctx, int excp)
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{
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generate_exception_err (ctx, excp, 0);
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}
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#if defined(CONFIG_USER_ONLY)
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#define op_ldst(name) gen_op_##name##_raw()
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#define OP_LD_TABLE(width)
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@ -1020,14 +1028,14 @@ static void gen_compute_branch (DisasContext *ctx, uint16_t opc,
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case OPC_BLEZ: /* 0 <= 0 */
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case OPC_BLEZL: /* 0 <= 0 likely */
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/* Always take */
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ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
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ctx->hflags |= MIPS_HFLAG_B;
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MIPS_DEBUG("balways");
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break;
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case OPC_BGEZAL: /* 0 >= 0 */
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case OPC_BGEZALL: /* 0 >= 0 likely */
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/* Always take and link */
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blink = 31;
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ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
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ctx->hflags |= MIPS_HFLAG_B;
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MIPS_DEBUG("balways and link");
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break;
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case OPC_BNE: /* rx != rx */
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@ -1053,21 +1061,21 @@ static void gen_compute_branch (DisasContext *ctx, uint16_t opc,
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gen_goto_tb(ctx, 0, ctx->pc + 4);
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return;
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case OPC_J:
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ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
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ctx->hflags |= MIPS_HFLAG_B;
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MIPS_DEBUG("j %08x", btarget);
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break;
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case OPC_JAL:
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blink = 31;
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ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
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ctx->hflags |= MIPS_HFLAG_B;
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MIPS_DEBUG("jal %08x", btarget);
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break;
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case OPC_JR:
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ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
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ctx->hflags |= MIPS_HFLAG_BR;
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MIPS_DEBUG("jr %s", regnames[rs]);
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break;
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case OPC_JALR:
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blink = rt;
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ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
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ctx->hflags |= MIPS_HFLAG_BR;
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MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
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break;
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default:
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@ -1144,14 +1152,14 @@ static void gen_compute_branch (DisasContext *ctx, uint16_t opc,
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blink = 31;
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MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
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not_likely:
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ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BC;
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ctx->hflags |= MIPS_HFLAG_BC;
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break;
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case OPC_BLTZALL:
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gen_op_ltz();
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blink = 31;
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MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
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likely:
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ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BL;
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ctx->hflags |= MIPS_HFLAG_BL;
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break;
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}
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gen_op_set_bcond();
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@ -1178,7 +1186,7 @@ static void gen_cp0 (DisasContext *ctx, uint16_t opc, int rt, int rd)
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "CP0 is not usable\n");
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}
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gen_op_raise_exception_err(EXCP_CpU, 0);
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generate_exception_err (ctx, EXCP_CpU, 0);
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return;
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}
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switch (opc) {
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@ -1236,7 +1244,15 @@ static void gen_cp0 (DisasContext *ctx, uint16_t opc, int rt, int rd)
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ctx->bstate = BS_EXCP;
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}
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break;
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/* XXX: TODO: WAIT */
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case OPC_WAIT:
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opn = "wait";
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/* If we get an exception, we want to restart at next instruction */
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ctx->pc += 4;
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save_cpu_state(ctx, 1);
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ctx->pc -= 4;
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gen_op_wait();
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ctx->bstate = BS_EXCP;
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break;
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default:
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
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@ -1292,7 +1308,7 @@ static void gen_blikely(DisasContext *ctx)
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int l1;
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l1 = gen_new_label();
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gen_op_jnz_T2(l1);
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gen_op_save_state(ctx->hflags & ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS));
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gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
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gen_goto_tb(ctx, 1, ctx->pc + 4);
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gen_set_label(l1);
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}
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@ -1304,8 +1320,7 @@ static void decode_opc (DisasContext *ctx)
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uint16_t op, op1;
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int16_t imm;
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if ((ctx->hflags & MIPS_HFLAG_DS) &&
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(ctx->hflags & MIPS_HFLAG_BL)) {
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if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
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/* Handle blikely not taken case */
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MIPS_DEBUG("blikely condition (%08x)", ctx->pc + 4);
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gen_blikely(ctx);
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@ -1361,9 +1376,16 @@ static void decode_opc (DisasContext *ctx)
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case 0x05: /* Pmon entry point */
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gen_op_pmon((ctx->opcode >> 6) & 0x1F);
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break;
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#if defined (MIPS_HAS_MOVCI)
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case 0x01: /* MOVCI */
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#if defined (MIPS_HAS_MOVCI)
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/* XXX */
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#else
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/* Not implemented */
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generate_exception_err (ctx, EXCP_CpU, 1);
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#endif
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break;
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#if defined (TARGET_MIPS64)
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case 0x14: /* MIPS64 specific opcodes */
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case 0x16:
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@ -1438,7 +1460,7 @@ static void decode_opc (DisasContext *ctx)
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gen_cp0(ctx, op1 | EXT_CP0, rt, rd);
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break;
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default:
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gen_cp0(ctx, (ctx->opcode & 0x1F) | EXT_CP0, rt, rd);
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gen_cp0(ctx, (ctx->opcode & 0x3F) | EXT_CP0, rt, rd);
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break;
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}
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break;
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@ -1467,23 +1489,35 @@ static void decode_opc (DisasContext *ctx)
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break;
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case 0x3F: /* HACK */
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break;
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#if defined(MIPS_USES_FPU)
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case 0x31 ... 0x32: /* Floating point load/store */
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case 0x35 ... 0x36:
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case 0x3A ... 0x3B:
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case 0x3D ... 0x3E:
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/* Not implemented */
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/* XXX: not correct */
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#endif
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/* Floating point. */
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case 0x31: /* LWC1 */
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case 0x35: /* LDC1 */
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case 0x39: /* SWC1 */
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case 0x3D: /* SDC1 */
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case 0x11: /* CP1 opcode */
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/* Not implemented */
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#if defined(MIPS_USES_FPU)
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/* XXX: not correct */
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#else
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generate_exception_err(ctx, EXCP_CpU, 1);
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#endif
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break;
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/* COP2. */
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case 0x32: /* LWC2 */
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case 0x36: /* LDC2 */
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case 0x3A: /* SWC2 */
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case 0x3E: /* SDC2 */
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case 0x12: /* CP2 opcode */
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/* Not implemented */
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/* XXX: not correct */
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generate_exception_err(ctx, EXCP_CpU, 2);
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break;
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case 0x13: /* CP3 opcode */
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/* Not implemented */
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/* XXX: not correct */
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generate_exception_err(ctx, EXCP_CpU, 3);
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break;
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#if defined (TARGET_MIPS64)
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case 0x18 ... 0x1B:
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case 0x27:
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@ -1497,21 +1531,15 @@ static void decode_opc (DisasContext *ctx)
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#endif
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case 0x1E:
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/* ASE specific */
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#if defined (MIPS_HAS_LSC)
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case 0x31: /* LWC1 */
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case 0x32: /* LWC2 */
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case 0x35: /* SDC1 */
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case 0x36: /* SDC2 */
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#endif
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default: /* Invalid */
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MIPS_INVAL("");
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generate_exception(ctx, EXCP_RI);
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break;
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}
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if (ctx->hflags & MIPS_HFLAG_DS) {
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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int hflags = ctx->hflags;
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/* Branches completion */
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ctx->hflags &= ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS);
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ctx->hflags &= ~MIPS_HFLAG_BMASK;
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ctx->bstate = BS_BRANCH;
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save_cpu_state(ctx, 0);
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switch (hflags & MIPS_HFLAG_BMASK) {
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@ -1557,16 +1585,20 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
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uint16_t *gen_opc_end;
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int j, lj = -1;
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if (search_pc && loglevel)
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fprintf (logfile, "search pc %d\n", search_pc);
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pc_start = tb->pc;
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gen_opc_ptr = gen_opc_buf;
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gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
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gen_opparam_ptr = gen_opparam_buf;
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nb_gen_labels = 0;
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ctx.pc = pc_start;
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ctx.saved_pc = -1;
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ctx.tb = tb;
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ctx.bstate = BS_NONE;
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/* Restore delay slot state */
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ctx.hflags = env->hflags;
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/* Restore delay slot state from the tb context. */
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ctx.hflags = tb->flags;
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ctx.saved_hflags = ctx.hflags;
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if (ctx.hflags & MIPS_HFLAG_BR) {
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gen_op_restore_breg_target();
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@ -1588,42 +1620,65 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
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#ifdef DEBUG_DISAS
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if (loglevel & CPU_LOG_TB_CPU) {
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fprintf(logfile, "------------------------------------------------\n");
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/* FIXME: This may print out stale hflags from env... */
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cpu_dump_state(env, logfile, fprintf, 0);
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}
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#endif
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#if defined MIPS_DEBUG_DISAS
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if (loglevel & CPU_LOG_TB_IN_ASM)
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fprintf(logfile, "\ntb %p super %d cond %04x %04x\n",
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tb, ctx.mem_idx, ctx.hflags, env->hflags);
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fprintf(logfile, "\ntb %p super %d cond %04x\n",
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tb, ctx.mem_idx, ctx.hflags);
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#endif
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while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
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if (env->nb_breakpoints > 0) {
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for(j = 0; j < env->nb_breakpoints; j++) {
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if (env->breakpoints[j] == ctx.pc) {
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save_cpu_state(ctxp, 1);
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ctx.bstate = BS_BRANCH;
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gen_op_debug();
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goto done_generating;
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}
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}
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}
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if (search_pc) {
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j = gen_opc_ptr - gen_opc_buf;
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save_cpu_state(ctxp, 1);
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if (lj < j) {
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lj++;
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while (lj < j)
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gen_opc_instr_start[lj++] = 0;
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gen_opc_pc[lj] = ctx.pc;
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gen_opc_instr_start[lj] = 1;
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}
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gen_opc_pc[lj] = ctx.pc;
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gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;
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gen_opc_instr_start[lj] = 1;
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}
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ctx.opcode = ldl_code(ctx.pc);
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decode_opc(&ctx);
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ctx.pc += 4;
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if (env->singlestep_enabled)
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break;
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if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
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break;
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#if defined (MIPS_SINGLE_STEP)
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break;
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#endif
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}
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if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
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if (env->singlestep_enabled) {
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save_cpu_state(ctxp, ctx.bstate == BS_NONE);
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gen_op_debug();
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goto done_generating;
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}
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else if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
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save_cpu_state(ctxp, 0);
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gen_goto_tb(&ctx, 0, ctx.pc);
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}
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gen_op_reset_T0();
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/* Generate the return instruction */
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gen_op_exit_tb();
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done_generating:
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*gen_opc_ptr = INDEX_op_end;
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if (search_pc) {
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j = gen_opc_ptr - gen_opc_buf;
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