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x86 queue, 2021-07-13
Bug fixes: * numa: Parse initiator= attribute before cpus= attribute (Michal Privoznik) * Fix CPUID level for AMD (Zhenwei Pi) * Suppress CPUID leaves not defined by the CPU vendor (Michael Roth) Cleanup: * Hyper-V feature handling cleanup (Vitaly Kuznetsov) -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEEWjIv1avE09usz9GqKAeTb5hNxaYFAmDtup0UHGVoYWJrb3N0 QHJlZGhhdC5jb20ACgkQKAeTb5hNxaamLBAAoMinHQ6sM8H9EgASYsIVy98iZG/O yAqEuyC00gjiibKs7+cxc6fFOAVSEUghRj2m0HZwbzENyMw7noDXJjHNWRt/suoC dWZRmnV9QMqtLV7S2+n1YXBrXL0MN1FtKguvM861tFuWE1nHivaTrgoaaRunZC9h P4dFSM+ToA06fkfiyX1POIBcaN0aishEKiNibRnF+B/8KSS6vWLjHzJptqDcN4B/ JDMG/gq5m26l0v9giqH6di60BUs1dI/YemO0YUckLHgsCQ7xCoFpOn0tAjKCz1c8 khQwcrZv25LxilKbBYIsBvv9sqaPmmNhUnsQ4DN0ZyA95S0Pirb4Mcs1W16Jrmj5 cjIZ+SdqzsBMwb4aAZIqM4YgU7v6xz/XBJ6VPPy8UlPAriKzAvcebuCN2f/FcJVR bExAoJbQ8OGqHVAi0cQk/fG7HP2sfayKvb3ObIXL5KffJq2KBRyyYlLKjQ9h4UvO 422yQFxlbcQM4TaLGIN1J0wwnM3SVpoGSQov9G97ClqkanCcLzbwGftwpw0z3+g5 uUpPrwQeKn4eskuowEnuZszOdonprKXXHkdPpYaeVBG4GCq6LBeNf+8D5fyfB2Yl 3Nu5fyG9msvMvx96OJUC8NcvGh8Z/r8JRBvrVH4d+L/wzuEI3N3wtxTeju2gVl9z bY4AY/psUkKAJSg= =ZM8P -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging x86 queue, 2021-07-13 Bug fixes: * numa: Parse initiator= attribute before cpus= attribute (Michal Privoznik) * Fix CPUID level for AMD (Zhenwei Pi) * Suppress CPUID leaves not defined by the CPU vendor (Michael Roth) Cleanup: * Hyper-V feature handling cleanup (Vitaly Kuznetsov) # gpg: Signature made Tue 13 Jul 2021 17:09:01 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost-gl/tags/x86-next-pull-request: numa: Parse initiator= attribute before cpus= attribute numa: Report expected initiator target/i386: Fix cpuid level for AMD target/i386: suppress CPUID leaves not defined by the CPU vendor i386: Hyper-V SynIC requires POST_MESSAGES/SIGNAL_EVENTS privileges i386: HV_HYPERCALL_AVAILABLE privilege bit is always needed i386: kill off hv_cpuid_check_and_set() i386: expand Hyper-V features during CPU feature expansion time i386: make hyperv_expand_features() return bool i386: hardcode supported eVMCS version to '1' i386: clarify 'hv-passthrough' behavior Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -170,7 +170,7 @@ Recommended: hv-frequencies
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3.16. hv-evmcs
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===============
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The enlightenment is nested specific, it targets Hyper-V on KVM guests. When
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enabled, it provides Enlightened VMCS feature to the guest. The feature
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enabled, it provides Enlightened VMCS version 1 feature to the guest. The feature
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implements paravirtualized protocol between L0 (KVM) and L1 (Hyper-V)
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hypervisors making L2 exits to the hypervisor faster. The feature is Intel-only.
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Note: some virtualization features (e.g. Posted Interrupts) are disabled when
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@ -209,8 +209,11 @@ In some cases (e.g. during development) it may make sense to use QEMU in
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'pass-through' mode and give Windows guests all enlightenments currently
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supported by KVM. This pass-through mode is enabled by "hv-passthrough" CPU
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flag.
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Note: enabling this flag effectively prevents migration as supported features
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may differ between target and destination.
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Note: "hv-passthrough" flag only enables enlightenments which are known to QEMU
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(have corresponding "hv-*" flag) and copies "hv-spinlocks="/"hv-vendor-id="
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values from KVM to QEMU. "hv-passthrough" overrides all other "hv-*" settings on
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the command line. Also, enabling this flag effectively prevents migration as the
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list of enabled enlightenments may differ between target and destination hosts.
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4. Useful links
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