motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-10 11:04:58 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

ppc/ppc405: QOM'ify CPC

Browse source 
The CPC controller is currently modeled as a DCR device.

Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <23393cb91a2c6c560a4461b3e9d1baa48ae28f74.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Cédric Le Goater 2022-08-17 17:08:20 +02:00 • committed by Daniel Henrique Barboza
parent 629cae6170
commit 4a7d2b7e5c
2 changed files with 95 additions and 81 deletions
Download patch file Download diff file Expand all files Collapse all files

35
hw/ppc/ppc405.h
View file

@ -63,6 +63,39 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
#define TYPE_PPC405_CPC "ppc405-cpc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
enum {
PPC405EP_CPU_CLK = 0,
PPC405EP_PLB_CLK = 1,
PPC405EP_OPB_CLK = 2,
PPC405EP_EBC_CLK = 3,
PPC405EP_MAL_CLK = 4,
PPC405EP_PCI_CLK = 5,
PPC405EP_UART0_CLK = 6,
PPC405EP_UART1_CLK = 7,
PPC405EP_CLK_NB = 8,
};
struct Ppc405CpcState {
Ppc4xxDcrDeviceState parent_obj;
uint32_t sysclk;
clk_setup_t clk_setup[PPC405EP_CLK_NB];
uint32_t boot;
uint32_t epctl;
uint32_t pllmr[2];
uint32_t ucr;
uint32_t srr;
uint32_t jtagid;
uint32_t pci;
/* Clock and power management */
uint32_t er;
uint32_t fr;
uint32_t sr;
};
#define TYPE_PPC405_SOC "ppc405-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
@ -78,9 +111,9 @@ struct Ppc405SoCState {
MemoryRegion *dram_mr;
hwaddr ram_size;
uint32_t sysclk;
PowerPCCPU cpu;
DeviceState *uic;
Ppc405CpcState cpc;
};
/* PowerPC 405 core */