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hw/arm/allwinner-r40: add SDRAM controller device

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Types of memory that the SDRAM controller supports are DDR2/DDR3
and capacities of up to 2GiB. This commit adds emulation support
of the Allwinner R40 SDRAM controller.

This driver only support 256M, 512M and 1024M memory now.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
qianfan Zhao 2023-06-06 10:19:32 +01:00 • committed by Peter Maydell
parent a954543092
commit 4a52ef61d9
7 changed files with 674 additions and 3 deletions
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13
include/hw/arm/allwinner-r40.h
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@ -26,6 +26,7 @@
#include "hw/intc/arm_gic.h"
#include "hw/sd/allwinner-sdhost.h"
#include "hw/misc/allwinner-r40-ccu.h"
#include "hw/misc/allwinner-r40-dramc.h"
#include "hw/i2c/allwinner-i2c.h"
#include "target/arm/cpu.h"
#include "sysemu/block-backend.h"
@ -54,7 +55,10 @@ enum {
AW_R40_DEV_GIC_CPU,
AW_R40_DEV_GIC_HYP,
AW_R40_DEV_GIC_VCPU,
AW_R40_DEV_SDRAM
AW_R40_DEV_SDRAM,
AW_R40_DEV_DRAMCOM,
AW_R40_DEV_DRAMCTL,
AW_R40_DEV_DRAMPHY,
};
#define AW_R40_NUM_CPUS (4)
@ -86,11 +90,18 @@ struct AwR40State {
DeviceState parent_obj;
/*< public >*/
/** Physical base address for start of RAM */
hwaddr ram_addr;
/** Total RAM size in megabytes */
uint32_t ram_size;
ARMCPU cpus[AW_R40_NUM_CPUS];
const hwaddr *memmap;
AwA10PITState timer;
AwSdHostState mmc[AW_R40_NUM_MMCS];
AwR40ClockCtlState ccu;
AwR40DramCtlState dramc;
AWI2CState i2c0;
GICState gic;
MemoryRegion sram_a1;