mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 00:03:54 -06:00
No functional changes:
- compilation warning fixes - make loglevel tests consistent - use cpu_abort instead of printf(...); exit git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2706 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer
parent
0405f55b57
commit
4a0577124a
6 changed files with 91 additions and 73 deletions
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@ -124,14 +124,14 @@ static int pte_check (mmu_ctx_t *ctx,
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(rw == 1 && (access & PAGE_WRITE))) {
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/* Access granted */
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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if (loglevel != 0)
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fprintf(logfile, "PTE access granted !\n");
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#endif
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ret = 0;
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} else {
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/* Access right violation */
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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if (loglevel != 0)
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fprintf(logfile, "PTE access rejected\n");
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#endif
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ret = -2;
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@ -214,10 +214,10 @@ static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
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target_ulong eaddr,
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int is_code, int match_epn)
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{
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#if !defined(FLUSH_ALL_TLBS)
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ppc6xx_tlb_t *tlb;
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int way, nr;
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#if !defined(FLUSH_ALL_TLBS)
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/* Invalidate ITLB + DTLB, all ways */
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for (way = 0; way < env->nb_ways; way++) {
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nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
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@ -331,7 +331,7 @@ static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
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if (best != -1) {
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done:
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#if defined (DEBUG_SOFTWARE_TLB)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
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ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
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}
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@ -353,7 +353,7 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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int ret = -1;
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
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type == ACCESS_CODE ? 'I' : 'D', virtual);
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}
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@ -369,7 +369,7 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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break;
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}
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
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type == ACCESS_CODE ? 'I' : 'D', virtual);
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}
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@ -382,7 +382,7 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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BEPIl = *BATu & 0x0FFE0000;
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bl = (*BATu & 0x00001FFC) << 15;
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
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" BATl 0x" ADDRX "\n",
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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@ -403,8 +403,8 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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if (*BATl & 0x00000002)
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ctx->prot = PAGE_WRITE | PAGE_READ;
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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fprintf(logfile, "BAT %d match: r 0x" ADDRX
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if (loglevel != 0) {
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fprintf(logfile, "BAT %d match: r 0x" PADDRX
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" prot=%c%c\n",
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i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
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ctx->prot & PAGE_WRITE ? 'W' : '-');
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@ -417,18 +417,20 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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}
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if (ret < 0) {
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#if defined (DEBUG_BATS)
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printf("no BAT match for 0x" ADDRX ":\n", virtual);
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for (i = 0; i < 4; i++) {
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BATu = &BATut[i];
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BATl = &BATlt[i];
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BEPIu = *BATu & 0xF0000000;
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BEPIl = *BATu & 0x0FFE0000;
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bl = (*BATu & 0x00001FFC) << 15;
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printf("%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
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" BATl 0x" ADDRX " \n\t"
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"0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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*BATu, *BATl, BEPIu, BEPIl, bl);
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if (loglevel != 0) {
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fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
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for (i = 0; i < 4; i++) {
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BATu = &BATut[i];
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BATl = &BATlt[i];
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BEPIu = *BATu & 0xF0000000;
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BEPIl = *BATu & 0x0FFE0000;
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bl = (*BATu & 0x00001FFC) << 15;
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fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
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" BATl 0x" ADDRX " \n\t"
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"0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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*BATu, *BATl, BEPIu, BEPIl, bl);
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}
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}
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#endif
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}
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@ -483,8 +485,8 @@ static int find_pte (mmu_ctx_t *ctx, int h, int rw)
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if (good != -1) {
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done:
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#if defined (DEBUG_MMU)
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if (loglevel > 0) {
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fprintf(logfile, "found PTE at addr 0x" ADDRX " prot=0x%01x "
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if (loglevel != 0) {
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fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
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"ret=%d\n",
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ctx->raddr, ctx->prot, ret);
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}
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@ -551,10 +553,11 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
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} else {
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#if defined (DEBUG_MMU)
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if (loglevel > 0) {
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fprintf(logfile, "0 sdr1=0x" ADDRX " vsid=0x%06x "
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"api=0x%04x hash=0x%07x pg_addr=0x" ADDRX "\n",
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sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
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if (loglevel != 0) {
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fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
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"api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
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sdr, (uint32_t)vsid, (uint32_t)pgidx,
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(uint32_t)hash, ctx->pg_addr[0]);
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}
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#endif
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/* Primary table lookup */
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@ -562,11 +565,12 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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if (ret < 0) {
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/* Secondary table lookup */
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#if defined (DEBUG_MMU)
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if (eaddr != 0xEFFFFFFF && loglevel > 0) {
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if (eaddr != 0xEFFFFFFF && loglevel != 0) {
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fprintf(logfile,
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"1 sdr1=0x" ADDRX " vsid=0x%06x api=0x%04x "
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"hash=0x%05x pg_addr=0x" ADDRX "\n",
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sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
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"1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
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"hash=0x%05x pg_addr=0x" PADDRX "\n",
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sdr, (uint32_t)vsid, (uint32_t)pgidx,
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(uint32_t)hash, ctx->pg_addr[1]);
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}
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#endif
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ret2 = find_pte(ctx, 1, rw);
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@ -576,14 +580,14 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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}
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} else {
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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if (loglevel != 0)
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fprintf(logfile, "No access allowed\n");
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#endif
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ret = -3;
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}
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} else {
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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if (loglevel != 0)
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fprintf(logfile, "direct store...\n");
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#endif
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/* Direct-store segment : absolutely *BUGGY* for now */
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@ -615,8 +619,6 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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fprintf(logfile, "ERROR: instruction should not need "
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"address translation\n");
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}
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printf("ERROR: instruction should not need "
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"address translation\n");
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return -4;
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}
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if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
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@ -663,12 +665,12 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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tlb = &env->tlb[i].tlbe;
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/* Check valid flag */
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if (!(tlb->prot & PAGE_VALID)) {
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if (loglevel)
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if (loglevel != 0)
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fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
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continue;
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}
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mask = ~(tlb->size - 1);
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if (loglevel) {
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if (loglevel != 0) {
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fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
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ADDRX " " ADDRX " %d\n",
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__func__, i, address, (int)env->spr[SPR_40x_PID],
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@ -683,7 +685,7 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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raddr = (tlb->RPN & mask) | (address & ~mask);
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zsel = (tlb->attr >> 4) & 0xF;
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zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
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if (loglevel) {
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if (loglevel != 0) {
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fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
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__func__, i, zsel, zpr, rw, tlb->attr);
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}
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@ -750,7 +752,7 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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}
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if (ret >= 0) {
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ctx->raddr = raddr;
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if (loglevel) {
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if (loglevel != 0) {
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fprintf(logfile, "%s: access granted " ADDRX " => " REGX
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" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
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ret);
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@ -758,7 +760,7 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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return 0;
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}
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}
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if (loglevel) {
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if (loglevel != 0) {
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fprintf(logfile, "%s: access refused " ADDRX " => " REGX
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" %d %d\n", __func__, address, raddr, ctx->prot,
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ret);
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@ -808,7 +810,7 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
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{
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int ret;
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#if 0
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "%s\n", __func__);
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}
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#endif
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@ -857,8 +859,8 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
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}
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}
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#if 0
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if (loglevel > 0) {
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fprintf(logfile, "%s address " ADDRX " => %d " ADDRX "\n",
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if (loglevel != 0) {
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fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
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__func__, eaddr, ret, ctx->raddr);
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}
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#endif
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@ -903,7 +905,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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is_user, is_softmmu);
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} else if (ret < 0) {
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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if (loglevel != 0)
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cpu_dump_state(env, logfile, fprintf, 0);
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#endif
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if (access_type == ACCESS_CODE) {
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@ -1564,7 +1566,7 @@ void do_interrupt (CPUState *env)
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idx = 2;
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msr &= ~0xFFFF0000;
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#if defined (DEBUG_EXCEPTIONS)
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if (loglevel) {
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if (loglevel != 0) {
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fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
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"\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
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}
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@ -1609,7 +1611,7 @@ void do_interrupt (CPUState *env)
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case EXCP_FP:
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if (msr_fe0 == 0 && msr_fe1 == 0) {
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#if defined (DEBUG_EXCEPTIONS)
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if (loglevel) {
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if (loglevel != 0) {
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fprintf(logfile, "Ignore floating point exception\n");
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}
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#endif
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@ -1625,7 +1627,7 @@ void do_interrupt (CPUState *env)
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break;
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case EXCP_INVAL:
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#if defined (DEBUG_EXCEPTIONS)
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if (loglevel) {
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if (loglevel != 0) {
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fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
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env->nip);
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}
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@ -1836,7 +1838,7 @@ void do_interrupt (CPUState *env)
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cmp = &env->spr[SPR_DCMP];
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}
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fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
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" H1 " ADDRX " H2 " ADDRX " " ADDRX "\n",
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" H1 " ADDRX " H2 " ADDRX " %08x\n",
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es, en, *miss, en, *cmp,
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env->spr[SPR_HASH1], env->spr[SPR_HASH2],
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env->error_code);
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@ -2153,7 +2155,21 @@ void cpu_dump_EA (target_ulong EA)
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f = stdout;
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return;
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}
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fprintf(f, "Memory access at address " TARGET_FMT_lx "\n", EA);
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fprintf(f, "Memory access at address " ADDRX "\n", EA);
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}
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void cpu_dump_rfi (target_ulong RA, target_ulong msr)
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{
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FILE *f;
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if (logfile) {
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f = logfile;
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} else {
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f = stdout;
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return;
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}
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fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
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RA, msr);
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}
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void cpu_ppc_reset (void *opaque)
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